Timing Report

Need help reading this report?

Design Name ataport_8255_01
Device, Speed (SpeedFile Version) XC95108, -7 (3.0)
Date Created Tue Sep 19 16:12:54 2006
Created By Timing Report Generator: version I.27
Copyright Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Cycle Time for DIOWn
Clock to Setup (tCYC) 12.000 ns.
Pad to Pad Delay (tPD) 12.500 ns.
Setup to Clock at the Pad (tSU) 5.500 ns.
Clock Pad to Output Pad Delay (tCO) 20.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
AUTO_TS_F2F 0.0 13.0 217 217
AUTO_TS_P2P 0.0 20.0 56 56
AUTO_TS_P2F 0.0 7.0 398 398
AUTO_TS_F2P 0.0 18.5 66 66


Constraint: TS1000

Description: PERIOD:PERIOD_DIOWn:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_DIORn:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DH0n.Q to DD<0>.D 0.000 13.000 -13.000
DH0n.Q to DD<1>.D 0.000 13.000 -13.000
DH0n.Q to DD<2>.D 0.000 13.000 -13.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DIOWn to REO 0.000 20.000 -20.000
DIOWn to SELECTEDn 0.000 19.000 -19.000
DIOWn to PORTA<0> 0.000 17.000 -17.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CS0n to DD<0>.D 0.000 7.000 -7.000
CS0n to DD<1>.D 0.000 7.000 -7.000
CS0n to DD<2>.D 0.000 7.000 -7.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DH0n.Q to REO 0.000 18.500 -18.500
DH1n.Q to REO 0.000 18.500 -18.500
DH2n.Q to REO 0.000 18.500 -18.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
DIOWn 83.333 Limited by Cycle Time for DIOWn
DIORn 125.000 Limited by Clock Pulse Width for DIORn

Setup/Hold Times for Clocks

Setup/Hold Times for Clock DIOWn
Source Pad Setup to clk (edge) Hold to clk (edge)
CS0n 4.500 0.000
CS1n 4.500 0.000
CSEL 4.500 0.000
DA0 4.500 0.000
DA1 4.500 0.000
DA2 4.500 0.000
DD<0> 4.500 0.000
DD<1> 4.500 0.000
DD<2> 4.500 0.000
DD<3> 4.500 0.000
DD<4> 4.500 0.000
DD<5> 4.500 0.000
DD<6> 4.500 0.000
DD<7> 4.500 0.000
DMACKn 4.500 0.000
DMARQ 4.500 0.000

Setup/Hold Times for Clock DIORn
Source Pad Setup to clk (edge) Hold to clk (edge)
CS0n 5.500 0.000
CS1n 5.500 0.000
CSEL 5.500 0.000
DA0 5.500 0.000
DA1 5.500 0.000
DA2 5.500 0.000
DMACKn 5.500 0.000
DMARQ 5.500 0.000
PORTA<0> 4.500 0.000
PORTA<1> 4.500 0.000
PORTA<2> 4.500 0.000
PORTA<3> 4.500 0.000
PORTA<4> 4.500 0.000
PORTA<5> 4.500 0.000
PORTA<6> 4.500 0.000
PORTA<7> 5.500 0.000
PORTB<0> 5.500 0.000
PORTB<1> 5.500 0.000
PORTB<2> 5.500 0.000
PORTB<3> 5.500 0.000
PORTB<4> 5.500 0.000
PORTB<5> 5.500 0.000
PORTB<6> 5.500 0.000
PORTB<7> 5.500 0.000
PORTC<0> 5.500 0.000
PORTC<1> 5.500 0.000
PORTC<2> 4.500 0.000
PORTC<3> 5.500 0.000
PORTC<4> 5.500 0.000
PORTC<5> 4.500 0.000
PORTC<6> 4.500 0.000
PORTC<7> 4.500 0.000


Clock to Pad Timing

Clock DIOWn to Pad
Destination Pad Clock (edge) to Pad
REO 20.000
SELECTEDn 19.000
PORTA<0> 17.000
PORTA<1> 17.000
PORTA<2> 17.000
PORTA<3> 17.000
PORTA<4> 17.000
PORTA<5> 17.000
PORTA<7> 17.000
PORTB<0> 17.000
PORTB<1> 17.000
PORTB<2> 17.000
PORTB<3> 17.000
PORTB<4> 17.000
PORTB<5> 17.000
PORTC<0> 17.000
PORTC<1> 17.000
PORTC<2> 17.000
PORTC<3> 17.000
PORTC<4> 17.000
PORTC<5> 17.000
PORTC<7> 17.000
PORTA<6> 13.000
PORTB<6> 13.000
PORTB<7> 13.000
PORTC<6> 13.000
DH0n 8.500
DH1n 8.500
DH2n 8.500
DH3n 8.500

Clock DIORn to Pad
Destination Pad Clock (edge) to Pad
DD<0> 8.500
DD<1> 8.500
DD<2> 8.500
DD<3> 8.500
DD<4> 8.500
DD<5> 8.500
DD<6> 8.500
DD<7> 8.500


Clock to Setup Times for Clocks

Clock to Setup for clock DIOWn
Source Destination Delay
DH0n.Q PORTA<1>.D 12.000
DH0n.Q PORTA<2>.D 12.000
DH0n.Q PORTA<3>.D 12.000
DH0n.Q PORTA<4>.D 12.000
DH0n.Q PORTA<5>.D 12.000
DH0n.Q PORTA<6>.D 12.000
DH0n.Q PORTA<7>.D 12.000
DH0n.Q PORTB<2>.D 12.000
DH0n.Q PORTB<3>.D 12.000
DH0n.Q PORTB<4>.D 12.000
DH0n.Q PORTB<5>.D 12.000
DH0n.Q PORTB<6>.D 12.000
DH0n.Q PORTB<7>.D 12.000
DH0n.Q PORTC<1>.D 12.000
DH0n.Q PORTC<2>.D 12.000
DH0n.Q PORTC<3>.D 12.000
DH0n.Q PORTC<4>.D 12.000
DH0n.Q PORTC<5>.D 12.000
DH0n.Q PORTC<6>.D 12.000
DH0n.Q PORTC<7>.D 12.000
DH0n.Q XLXN_144.D 12.000
DH0n.Q XLXN_145.D 12.000
DH0n.Q XLXN_146.D 12.000
DH0n.Q XLXN_147.D 12.000
DH1n.Q PORTA<0>.D 12.000
DH1n.Q PORTA<2>.D 12.000
DH1n.Q PORTA<4>.D 12.000
DH1n.Q PORTA<6>.D 12.000
DH1n.Q PORTA<7>.D 12.000
DH1n.Q PORTB<0>.D 12.000
DH1n.Q PORTB<1>.D 12.000
DH1n.Q PORTB<2>.D 12.000
DH1n.Q PORTB<3>.D 12.000
DH1n.Q PORTB<4>.D 12.000
DH1n.Q PORTB<5>.D 12.000
DH1n.Q PORTB<6>.D 12.000
DH1n.Q PORTB<7>.D 12.000
DH1n.Q PORTC<0>.D 12.000
DH1n.Q PORTC<2>.D 12.000
DH1n.Q PORTC<4>.D 12.000
DH1n.Q PORTC<5>.D 12.000
DH1n.Q PORTC<6>.D 12.000
DH1n.Q PORTC<7>.D 12.000
DH1n.Q XLXN_144.D 12.000
DH1n.Q XLXN_145.D 12.000
DH1n.Q XLXN_146.D 12.000
DH1n.Q XLXN_147.D 12.000
DH2n.Q PORTA<0>.D 12.000
DH2n.Q PORTA<1>.D 12.000
DH2n.Q PORTA<3>.D 12.000
DH2n.Q PORTA<4>.D 12.000
DH2n.Q PORTA<5>.D 12.000
DH2n.Q PORTA<6>.D 12.000
DH2n.Q PORTA<7>.D 12.000
DH2n.Q PORTB<0>.D 12.000
DH2n.Q PORTB<1>.D 12.000
DH2n.Q PORTB<4>.D 12.000
DH2n.Q PORTB<5>.D 12.000
DH2n.Q PORTB<6>.D 12.000
DH2n.Q PORTB<7>.D 12.000
DH2n.Q PORTC<0>.D 12.000
DH2n.Q PORTC<1>.D 12.000
DH2n.Q PORTC<3>.D 12.000
DH2n.Q PORTC<4>.D 12.000
DH2n.Q PORTC<5>.D 12.000
DH2n.Q PORTC<6>.D 12.000
DH2n.Q PORTC<7>.D 12.000
DH2n.Q XLXN_144.D 12.000
DH2n.Q XLXN_145.D 12.000
DH2n.Q XLXN_146.D 12.000
DH2n.Q XLXN_147.D 12.000
DH3n.Q PORTA<0>.D 12.000
DH3n.Q PORTA<2>.D 12.000
DH3n.Q PORTA<4>.D 12.000
DH3n.Q PORTA<6>.D 12.000
DH3n.Q PORTA<7>.D 12.000
DH3n.Q PORTB<0>.D 12.000
DH3n.Q PORTB<1>.D 12.000
DH3n.Q PORTB<2>.D 12.000
DH3n.Q PORTB<3>.D 12.000
DH3n.Q PORTB<4>.D 12.000
DH3n.Q PORTB<5>.D 12.000
DH3n.Q PORTB<6>.D 12.000
DH3n.Q PORTB<7>.D 12.000
DH3n.Q PORTC<0>.D 12.000
DH3n.Q PORTC<2>.D 12.000
DH3n.Q PORTC<4>.D 12.000
DH3n.Q PORTC<5>.D 12.000
DH3n.Q PORTC<6>.D 12.000
DH3n.Q PORTC<7>.D 12.000
DH3n.Q XLXN_144.D 12.000
DH3n.Q XLXN_145.D 12.000
DH3n.Q XLXN_146.D 12.000
DH3n.Q XLXN_147.D 12.000
XLXI_81/XLXN_43.Q PORTA<0>.D 12.000
XLXI_81/XLXN_43.Q PORTA<1>.D 12.000
XLXI_81/XLXN_43.Q PORTA<2>.D 12.000
XLXI_81/XLXN_43.Q PORTA<3>.D 12.000
XLXI_81/XLXN_43.Q PORTA<5>.D 12.000
XLXI_81/XLXN_43.Q PORTA<6>.D 12.000
XLXI_81/XLXN_43.Q PORTA<7>.D 12.000
XLXI_81/XLXN_43.Q PORTB<0>.D 12.000
XLXI_81/XLXN_43.Q PORTB<1>.D 12.000
XLXI_81/XLXN_43.Q PORTB<2>.D 12.000
XLXI_81/XLXN_43.Q PORTB<3>.D 12.000
XLXI_81/XLXN_43.Q PORTB<6>.D 12.000
XLXI_81/XLXN_43.Q PORTB<7>.D 12.000
XLXI_81/XLXN_43.Q PORTC<0>.D 12.000
XLXI_81/XLXN_43.Q PORTC<1>.D 12.000
XLXI_81/XLXN_43.Q PORTC<2>.D 12.000
XLXI_81/XLXN_43.Q PORTC<3>.D 12.000
XLXI_81/XLXN_43.Q PORTC<5>.D 12.000
XLXI_81/XLXN_43.Q PORTC<6>.D 12.000
XLXI_81/XLXN_43.Q PORTC<7>.D 12.000
XLXI_81/XLXN_43.Q XLXN_144.D 12.000
XLXI_81/XLXN_43.Q XLXN_145.D 12.000
XLXI_81/XLXN_43.Q XLXN_146.D 12.000
XLXI_81/XLXN_43.Q XLXN_147.D 12.000
DH0n.Q DH0n.D 8.000
DH0n.Q PORTA<0>.D 8.000
DH0n.Q PORTB<0>.D 8.000
DH0n.Q PORTB<1>.D 8.000
DH0n.Q PORTC<0>.D 8.000
DH1n.Q DH1n.D 8.000
DH1n.Q PORTA<1>.D 8.000
DH1n.Q PORTA<3>.D 8.000
DH1n.Q PORTA<5>.D 8.000
DH1n.Q PORTC<1>.D 8.000
DH1n.Q PORTC<3>.D 8.000
DH2n.Q DH2n.D 8.000
DH2n.Q PORTA<2>.D 8.000
DH2n.Q PORTB<2>.D 8.000
DH2n.Q PORTB<3>.D 8.000
DH2n.Q PORTC<2>.D 8.000
DH3n.Q DH3n.D 8.000
DH3n.Q PORTA<1>.D 8.000
DH3n.Q PORTA<3>.D 8.000
DH3n.Q PORTA<5>.D 8.000
DH3n.Q PORTC<1>.D 8.000
DH3n.Q PORTC<3>.D 8.000
PORTA<0>.Q PORTA<0>.D 8.000
PORTA<1>.Q PORTA<1>.D 8.000
PORTA<2>.Q PORTA<2>.D 8.000
PORTA<3>.Q PORTA<3>.D 8.000
PORTA<4>.Q PORTA<4>.D 8.000
PORTA<5>.Q PORTA<5>.D 8.000
PORTA<6>.Q PORTA<6>.D 8.000
PORTA<7>.Q PORTA<7>.D 8.000
PORTB<0>.Q PORTB<0>.D 8.000
PORTB<1>.Q PORTB<1>.D 8.000
PORTB<2>.Q PORTB<2>.D 8.000
PORTB<3>.Q PORTB<3>.D 8.000
PORTB<4>.Q PORTB<4>.D 8.000
PORTB<5>.Q PORTB<5>.D 8.000
PORTB<6>.Q PORTB<6>.D 8.000
PORTB<7>.Q PORTB<7>.D 8.000
PORTC<0>.Q PORTC<0>.D 8.000
PORTC<1>.Q PORTC<1>.D 8.000
PORTC<2>.Q PORTC<2>.D 8.000
PORTC<3>.Q PORTC<3>.D 8.000
PORTC<4>.Q PORTC<4>.D 8.000
PORTC<5>.Q PORTC<5>.D 8.000
PORTC<6>.Q PORTC<6>.D 8.000
PORTC<7>.Q PORTC<7>.D 8.000
XLXI_81/XLXN_43.Q PORTA<4>.D 8.000
XLXI_81/XLXN_43.Q PORTB<4>.D 8.000
XLXI_81/XLXN_43.Q PORTB<5>.D 8.000
XLXI_81/XLXN_43.Q PORTC<4>.D 8.000
XLXI_81/XLXN_43.Q XLXI_81/XLXN_43.D 8.000
XLXN_144.Q XLXN_144.D 8.000
XLXN_145.Q XLXN_145.D 8.000
XLXN_146.Q XLXN_146.D 8.000
XLXN_147.Q XLXN_147.D 8.000


Pad to Pad List

Source Pad Destination Pad Delay
CS0n REO 12.500
CS1n REO 12.500
CSEL REO 12.500
DA2 REO 12.500
DIORn REO 12.500
DMACKn REO 12.500
DMARQ REO 12.500
CSEL SELECTEDn 11.500
DA0 REO 11.500
DA1 REO 11.500
REI DD<0> 5.500
REI DD<1> 5.500
REI DD<2> 5.500
REI DD<3> 5.500
REI DD<4> 5.500
REI DD<5> 5.500
REI DD<6> 5.500
REI DD<7> 5.500



Number of paths analyzed: 737
Number of Timing errors: 737
Analysis Completed: Tue Sep 19 16:12:54 2006