cpldfit: version I.27 Xilinx Inc. Fitter Report Design Name: ataport_8255_01 Date: 9-19-2006, 4:12PM Device Used: XC95108-7-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 43 /108 ( 40%) 212 /540 ( 39%) 164/216 ( 76%) 41 /108 ( 38%) 50 /69 ( 72%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 6/18 25/36 25 28/90 6/12 FB2 6/18 25/36 25 30/90 6/12 FB3 7/18 28/36 28 38/90 6/12 FB4 10/18 33/36 33 50/90 6/11 FB5 8/18 26/36 26 35/90 8/11 FB6 6/18 27/36 27 31/90 6/11 ----- ----- ----- ----- 43/108 164/216 212/540 38/69 * - Resource is exhausted ** Global Control Resources ** The complement of 'DIORn' mapped onto global clock net GCK1. Signal 'DIOWn' mapped onto global clock net GCK2. Signal 'REI' mapped onto global output enable net GTS1. The complement of 'RESETn' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 8 8 | I/O : 46 63 Output : 6 6 | GCK/IO : 2 3 Bidirectional : 32 32 | GTS/IO : 1 2 GCK : 2 2 | GSR/IO : 1 1 GTS : 1 1 | GSR : 1 1 | ---- ---- Total 50 50 ** Power Data ** There are 43 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 38 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State PORTB<0> 5 16 FB1_5 3 I/O I/O STD SLOW RESET PORTB<1> 5 16 FB1_6 4 I/O I/O STD SLOW RESET PORTA<0> 5 16 FB1_8 5 I/O I/O STD SLOW RESET PORTC<0> 5 16 FB1_11 7 I/O I/O STD SLOW RESET DD<5> 6 16 FB1_15 11 I/O I/O STD SLOW RESET DH0n 2 9 FB1_17 13 I/O O STD SLOW SET PORTB<2> 5 16 FB2_6 75 I/O I/O STD SLOW RESET PORTB<3> 5 16 FB2_11 79 I/O I/O STD SLOW RESET PORTA<2> 5 16 FB2_12 80 I/O I/O STD SLOW RESET PORTC<2> 5 16 FB2_15 82 I/O I/O STD SLOW RESET DD<4> 8 17 FB2_16 83 I/O I/O STD SLOW RESET DH2n 2 9 FB2_17 84 I/O O STD SLOW SET PORTB<4> 5 16 FB3_5 17 I/O I/O STD SLOW RESET PORTB<5> 5 16 FB3_6 18 I/O I/O STD SLOW RESET PORTA<4> 5 16 FB3_8 19 I/O I/O STD SLOW RESET PORTC<4> 5 16 FB3_11 21 I/O I/O STD SLOW RESET DD<1> 8 17 FB3_12 23 I/O I/O STD SLOW RESET DD<7> 8 16 FB3_14 24 I/O I/O STD SLOW RESET PORTB<6> 5 16 FB4_5 61 I/O I/O STD SLOW RESET PORTB<7> 5 16 FB4_6 62 I/O I/O STD SLOW RESET PORTA<6> 5 16 FB4_8 63 I/O I/O STD SLOW RESET PORTC<6> 5 16 FB4_11 66 I/O I/O STD SLOW RESET DD<3> 8 17 FB4_12 67 I/O I/O STD SLOW RESET REO 6 14 FB4_14 68 I/O O STD SLOW PORTA<1> 5 16 FB5_2 32 I/O I/O STD SLOW RESET PORTA<3> 5 16 FB5_3 33 I/O I/O STD SLOW RESET PORTA<5> 5 16 FB5_5 34 I/O I/O STD SLOW RESET PORTC<1> 5 16 FB5_9 37 I/O I/O STD SLOW RESET PORTC<3> 5 16 FB5_11 39 I/O I/O STD SLOW RESET DD<6> 6 16 FB5_12 40 I/O I/O STD SLOW RESET DH1n 2 9 FB5_14 41 I/O O STD SLOW SET DH3n 2 9 FB5_15 43 I/O O STD SLOW SET PORTA<7> 5 16 FB6_2 45 I/O I/O STD SLOW RESET PORTC<5> 5 16 FB6_6 48 I/O I/O STD SLOW RESET PORTC<7> 5 16 FB6_8 50 I/O I/O STD SLOW RESET DD<0> 8 17 FB6_9 51 I/O I/O STD SLOW RESET DD<2> 6 16 FB6_11 52 I/O I/O STD SLOW RESET SELECTEDn 2 2 FB6_12 53 I/O O STD SLOW ** 5 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXI_81/XLXN_43 2 9 FB3_18 STD RESET XLXN_147 4 19 FB4_15 STD RESET XLXN_146 4 19 FB4_16 STD RESET XLXN_145 4 19 FB4_17 STD RESET XLXN_144 4 19 FB4_18 STD RESET ** 12 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use DIORn FB1_12 9 GCK/I/O GCK/I DIOWn FB1_14 10 GCK/I/O GCK RESETn FB2_5 74 GSR/I/O GSR REI FB2_8 76 GTS/I/O GTS DA2 FB3_16 26 I/O I CSEL FB3_17 31 I/O I CS1n FB4_15 69 I/O I DA1 FB4_17 70 I/O I DA0 FB5_17 44 I/O I CS0n FB6_14 54 I/O I DMARQ FB6_15 55 I/O I DMACKn FB6_17 56 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 25/11 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O (unused) 0 0 0 5 FB1_3 2 I/O (unused) 0 0 0 5 FB1_4 (b) PORTB<0> 5 0 0 0 FB1_5 3 I/O I/O PORTB<1> 5 0 0 0 FB1_6 4 I/O I/O (unused) 0 0 0 5 FB1_7 (b) PORTA<0> 5 0 0 0 FB1_8 5 I/O I/O (unused) 0 0 0 5 FB1_9 6 I/O (unused) 0 0 0 5 FB1_10 (b) PORTC<0> 5 0 0 0 FB1_11 7 I/O I/O (unused) 0 0 0 5 FB1_12 9 GCK/I/O GCK/I (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 \/1 4 FB1_14 10 GCK/I/O GCK DD<5> 6 1<- 0 0 FB1_15 11 I/O I/O (unused) 0 0 0 5 FB1_16 12 GCK/I/O DH0n 2 0 0 3 FB1_17 13 I/O O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: DA0 10: DD<0>.PIN 18: CS0n 2: DA1 11: DD<1>.PIN 19: XLXI_81/XLXN_43 3: DA2 12: XLXI_16/Q<0>.LFBK 20: XLXI_81/XLXN_447.LFBK 4: PORTA<5>.PIN 13: XLXI_18/Q<0>.LFBK 21: DMACKn 5: PORTB<5>.PIN 14: XLXI_18/Q<1>.LFBK 22: CS1n 6: PORTC<5>.PIN 15: XLXI_19/Q<0>.LFBK 23: XLXN_144 7: DH1n 16: CSEL 24: XLXN_146 8: DH2n 17: DMARQ 25: XLXN_147 9: DH3n Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs PORTB<0> XXX...XXXX..X..XXXXXXX.X................ 16 16 PORTB<1> XXX...XXX.X..X.XXXXXXX.X................ 16 16 PORTA<0> XXX...XXXX.X...XXXXXXXX................. 16 16 PORTC<0> XXX...XXXX....XXXXXXXX..X............... 16 16 DD<5> XXXXXXXXX......XXXXXXX.................. 16 16 DH0n XXX......X......XX.XXX.................. 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 25/11 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 71 I/O (unused) 0 0 0 5 FB2_3 72 I/O (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 74 GSR/I/O GSR PORTB<2> 5 0 0 0 FB2_6 75 I/O I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 76 GTS/I/O GTS (unused) 0 0 0 5 FB2_9 77 GTS/I/O (unused) 0 0 0 5 FB2_10 (b) PORTB<3> 5 0 0 0 FB2_11 79 I/O I/O PORTA<2> 5 0 0 0 FB2_12 80 I/O I/O (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 81 I/O PORTC<2> 5 0 0 0 FB2_15 82 I/O I/O DD<4> 8 3<- 0 0 FB2_16 83 I/O I/O DH2n 2 0 /\3 0 FB2_17 84 I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: DA0 10: DD<2>.PIN 18: CS0n 2: DA1 11: DD<3>.PIN 19: XLXI_81/XLXN_43 3: DA2 12: XLXI_16/Q<2>.LFBK 20: XLXI_81/XLXN_449.LFBK 4: PORTA<4>.PIN 13: XLXI_18/Q<2>.LFBK 21: DMACKn 5: PORTB<4>.PIN 14: XLXI_18/Q<3>.LFBK 22: CS1n 6: PORTC<4>.PIN 15: XLXI_19/Q<2>.LFBK 23: XLXN_144 7: DH0n 16: CSEL 24: XLXN_146 8: DH1n 17: DMARQ 25: XLXN_147 9: DH3n Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs PORTB<2> XXX...XXXX..X..XXXXXXX.X................ 16 16 PORTB<3> XXX...XXX.X..X.XXXXXXX.X................ 16 16 PORTA<2> XXX...XXXX.X...XXXXXXXX................. 16 16 PORTC<2> XXX...XXXX....XXXXXXXX..X............... 16 16 DD<4> XXXXXXXXX......XXXXXXXX................. 17 17 DH2n XXX......X......XX.XXX.................. 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 28/8 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 14 I/O (unused) 0 0 0 5 FB3_3 15 I/O (unused) 0 0 0 5 FB3_4 (b) PORTB<4> 5 0 0 0 FB3_5 17 I/O I/O PORTB<5> 5 0 0 0 FB3_6 18 I/O I/O (unused) 0 0 0 5 FB3_7 (b) PORTA<4> 5 0 0 0 FB3_8 19 I/O I/O (unused) 0 0 0 5 FB3_9 20 I/O (unused) 0 0 0 5 FB3_10 (b) PORTC<4> 5 0 0 0 FB3_11 21 I/O I/O DD<1> 8 3<- 0 0 FB3_12 23 I/O I/O (unused) 0 0 /\3 2 FB3_13 (b) (b) DD<7> 8 3<- 0 0 FB3_14 24 I/O I/O (unused) 0 0 /\3 2 FB3_15 25 I/O (b) (unused) 0 0 0 5 FB3_16 26 I/O I (unused) 0 0 0 5 FB3_17 31 I/O I XLXI_81/XLXN_43 2 0 0 3 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: DA0 11: DH1n 20: CSEL 2: DA1 12: DH2n 21: DMARQ 3: DA2 13: DH3n 22: CS0n 4: PORTA<1>.PIN 14: DD<4>.PIN 23: XLXI_81/XLXN_43.LFBK 5: PORTA<7>.PIN 15: DD<5>.PIN 24: DMACKn 6: PORTB<1>.PIN 16: XLXI_16/Q<4>.LFBK 25: CS1n 7: PORTB<7>.PIN 17: XLXI_18/Q<4>.LFBK 26: XLXN_144 8: PORTC<1>.PIN 18: XLXI_18/Q<5>.LFBK 27: XLXN_145 9: PORTC<7>.PIN 19: XLXI_19/Q<4>.LFBK 28: XLXN_146 10: DH0n Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs PORTB<4> XXX......XXXXX..X..XXXXXX..X............ 16 16 PORTB<5> XXX......XXXX.X..X.XXXXXX..X............ 16 16 PORTA<4> XXX......XXXXX.X...XXXXXXX.............. 16 16 PORTC<4> XXX......XXXXX....XXXXXXX.X............. 16 16 DD<1> XXXX.X.X.XXXX......XXXXXX..X............ 17 17 DD<7> XXX.X.X.XXXXX......XXXXXX............... 16 16 XLXI_81/XLXN_43 XXX..........X......XXXXX............... 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 33/3 Number of signals used by logic mapping into function block: 33 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 57 I/O (unused) 0 0 0 5 FB4_3 58 I/O (unused) 0 0 0 5 FB4_4 (b) PORTB<6> 5 0 0 0 FB4_5 61 I/O I/O PORTB<7> 5 0 0 0 FB4_6 62 I/O I/O (unused) 0 0 0 5 FB4_7 (b) PORTA<6> 5 0 0 0 FB4_8 63 I/O I/O (unused) 0 0 0 5 FB4_9 65 I/O (unused) 0 0 0 5 FB4_10 (b) PORTC<6> 5 0 0 0 FB4_11 66 I/O I/O DD<3> 8 3<- 0 0 FB4_12 67 I/O I/O (unused) 0 0 /\3 2 FB4_13 (b) (b) REO 6 1<- 0 0 FB4_14 68 I/O O XLXN_147 4 0 /\1 0 FB4_15 69 I/O I XLXN_146 4 0 0 1 FB4_16 (b) (b) XLXN_145 4 0 0 1 FB4_17 70 I/O I XLXN_144 4 0 0 1 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: DA0 12: DD<1>.PIN 23: DIORn 2: DA1 13: DD<2>.PIN 24: CSEL 3: DA2 14: DD<3>.PIN 25: DMARQ 4: PORTA<3>.PIN 15: DD<4>.PIN 26: CS0n 5: PORTB<3>.PIN 16: DD<5>.PIN 27: XLXI_81/XLXN_43 6: PORTC<3>.PIN 17: DD<6>.PIN 28: DMACKn 7: DH0n 18: DD<7>.PIN 29: CS1n 8: DH1n 19: XLXI_16/Q<6>.LFBK 30: XLXN_144.LFBK 9: DH2n 20: XLXI_18/Q<6>.LFBK 31: XLXN_145.LFBK 10: DH3n 21: XLXI_18/Q<7>.LFBK 32: XLXN_146.LFBK 11: DD<0>.PIN 22: XLXI_19/Q<6>.LFBK 33: XLXN_147.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs PORTB<6> XXX...XXXX......X..X...XXXXXX..X........ 16 16 PORTB<7> XXX...XXXX.......X..X..XXXXXX..X........ 16 16 PORTA<6> XXX...XXXX......X.X....XXXXXXX.......... 16 16 PORTC<6> XXX...XXXX......X....X.XXXXXX.X......... 16 16 DD<3> XXXXXXXXXX.............XXXXXX.X......... 17 17 REO XXX...XXXX............XXXXXXX........... 14 14 XLXN_147 XXX...XXXXX.X..XXX.....XXXXXX...X....... 19 19 XLXN_146 XXX...XXXX.XX..XXX.....XXXXXX..X........ 19 19 XLXN_145 XXX...XXXX..XX.XXX.....XXXXXX.X......... 19 19 XLXN_144 XXX...XXXX..X.XXXX.....XXXXXXX.......... 19 19 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 26/10 Number of signals used by logic mapping into function block: 26 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) PORTA<1> 5 0 0 0 FB5_2 32 I/O I/O PORTA<3> 5 0 0 0 FB5_3 33 I/O I/O (unused) 0 0 0 5 FB5_4 (b) PORTA<5> 5 0 0 0 FB5_5 34 I/O I/O (unused) 0 0 0 5 FB5_6 35 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 36 I/O PORTC<1> 5 0 0 0 FB5_9 37 I/O I/O (unused) 0 0 0 5 FB5_10 (b) PORTC<3> 5 0 0 0 FB5_11 39 I/O I/O DD<6> 6 1<- 0 0 FB5_12 40 I/O I/O (unused) 0 0 /\1 4 FB5_13 (b) (b) DH1n 2 0 0 3 FB5_14 41 I/O O DH3n 2 0 0 3 FB5_15 43 I/O O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O I (unused) 0 0 0 5 FB5_18 (b) Signals Used by Logic in Function Block 1: DA0 10: DD<3>.PIN 19: CS0n 2: DA1 11: DD<5>.PIN 20: XLXI_81/XLXN_43 3: DA2 12: XLXI_16/Q<1>.LFBK 21: XLXI_81/XLXN_448.LFBK 4: PORTA<6>.PIN 13: XLXI_16/Q<3>.LFBK 22: XLXI_81/XLXN_450.LFBK 5: PORTB<6>.PIN 14: XLXI_16/Q<5>.LFBK 23: DMACKn 6: PORTC<6>.PIN 15: XLXI_19/Q<1>.LFBK 24: CS1n 7: DH0n 16: XLXI_19/Q<3>.LFBK 25: XLXN_144 8: DH2n 17: CSEL 26: XLXN_147 9: DD<1>.PIN 18: DMARQ Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs PORTA<1> XXX...XXX..X....XXXXXXXXX............... 16 16 PORTA<3> XXX...XX.X..X...XXXXXXXXX............... 16 16 PORTA<5> XXX...XX..X..X..XXXXXXXXX............... 16 16 PORTC<1> XXX...XXX.....X.XXXXXXXX.X.............. 16 16 PORTC<3> XXX...XX.X.....XXXXXXXXX.X.............. 16 16 DD<6> XXXXXXXX........XXXXXXXX................ 16 16 DH1n XXX.....X........XX.X.XX................ 9 9 DH3n XXX......X.......XX..XXX................ 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 27/9 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) PORTA<7> 5 0 0 0 FB6_2 45 I/O I/O (unused) 0 0 0 5 FB6_3 46 I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 47 I/O PORTC<5> 5 0 0 0 FB6_6 48 I/O I/O (unused) 0 0 0 5 FB6_7 (b) PORTC<7> 5 0 0 0 FB6_8 50 I/O I/O DD<0> 8 3<- 0 0 FB6_9 51 I/O I/O (unused) 0 0 /\3 2 FB6_10 (b) (b) DD<2> 6 1<- 0 0 FB6_11 52 I/O I/O SELECTEDn 2 0 /\1 2 FB6_12 53 I/O O (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 54 I/O I (unused) 0 0 0 5 FB6_15 55 I/O I (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 56 I/O I (unused) 0 0 0 5 FB6_18 (b) Signals Used by Logic in Function Block 1: DA0 10: DH0n 19: CSEL 2: DA1 11: DH1n 20: DMARQ 3: DA2 12: DH2n 21: CS0n 4: PORTA<0>.PIN 13: DH3n 22: XLXI_81/XLXN_43 5: PORTA<2>.PIN 14: DD<5>.PIN 23: DMACKn 6: PORTB<0>.PIN 15: DD<7>.PIN 24: CS1n 7: PORTB<2>.PIN 16: XLXI_16/Q<7>.LFBK 25: XLXN_144 8: PORTC<0>.PIN 17: XLXI_19/Q<5>.LFBK 26: XLXN_145 9: PORTC<2>.PIN 18: XLXI_19/Q<7>.LFBK 27: XLXN_147 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs PORTA<7> XXX......XXXX.XX..XXXXXXX............... 16 16 PORTC<5> XXX......XXXXX..X.XXXXXX.X.............. 16 16 PORTC<7> XXX......XXXX.X..XXXXXXX.X.............. 16 16 DD<0> XXXX.X.X.XXXX.....XXXXXX..X............. 17 17 DD<2> XXX.X.X.XXXXX.....XXXXXX................ 16 16 SELECTEDn ..................X..X.................. 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_DD0: FDCPE port map (DD_I(0),DD(0),NOT DIORn,'0','0'); DD(0) <= ((EXP5_.EXP) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXN_147 AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXN_147 AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTA(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTA(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTC(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL)); FDCPE_DD1: FDCPE port map (DD_I(1),DD(1),NOT DIORn,'0','0'); DD(1) <= ((EXP1_.EXP) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXN_146 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXN_146 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND PORTA(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND PORTA(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND PORTC(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK)); FDCPE_DD2: FDCPE port map (DD_I(2),DD(2),NOT DIORn,'0','0'); DD(2) <= ((XLXI_81/XLXN_451.EXP) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTB(2).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTA(2).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTA(2).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTC(2).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTC(2).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL)); FDCPE_DD3: FDCPE port map (DD_I(3),DD(3),NOT DIORn,'0','0'); DD(3) <= ((EXP3_.EXP) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXN_145.LFBK) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXN_145.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTA(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTA(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTC(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL)); FDCPE_DD4: FDCPE port map (DD_I(4),DD(4),NOT DIORn,'0','0'); DD(4) <= ((XLXI_81/XLXN_449.EXP) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXN_144 AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXN_144 AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTA(4).PIN AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTA(4).PIN AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTC(4).PIN AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK)); FDCPE_DD5: FDCPE port map (DD_I(5),DD(5),NOT DIORn,'0','0'); DD(5) <= ((EXP0_.EXP) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTB(5).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTA(5).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTA(5).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTC(5).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTC(5).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK)); FDCPE_DD6: FDCPE port map (DD_I(6),DD(6),NOT DIORn,'0','0'); DD(6) <= ((EXP4_.EXP) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTB(6).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTA(6).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTA(6).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND PORTC(6).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND PORTC(6).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK)); FDCPE_DD7: FDCPE port map (DD_I(7),DD(7),NOT DIORn,'0','0'); DD(7) <= ((EXP2_.EXP) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK) OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK) OR (NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND PORTC(7).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK) OR (NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND PORTC(7).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND PORTA(7).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK)); FTCPE_DH0n: FTCPE port map (DH0n,DH0n_T,DIOWn,'0',NOT RESETn); DH0n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(0).PIN AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(0).PIN AND NOT XLXI_81/XLXN_447.LFBK)); FTCPE_DH1n: FTCPE port map (DH1n,DH1n_T,DIOWn,'0',NOT RESETn); DH1n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(1).PIN AND XLXI_81/XLXN_448.LFBK) OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(1).PIN AND NOT XLXI_81/XLXN_448.LFBK)); FTCPE_DH2n: FTCPE port map (DH2n,DH2n_T,DIOWn,'0',NOT RESETn); DH2n_T <= ((DD(2).PIN AND NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_449.LFBK) OR (NOT DD(2).PIN AND NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_449.LFBK)); FTCPE_DH3n: FTCPE port map (DH3n,DH3n_T,DIOWn,'0',NOT RESETn); DH3n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(3).PIN AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(3).PIN AND NOT XLXI_81/XLXN_450.LFBK)); FTCPE_PORTA0: FTCPE port map (PORTA_I(0),PORTA_T(0),DIOWn,NOT RESETn,'0'); PORTA_T(0) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_16/Q(0).LFBK AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_16/Q(0).LFBK AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_16/Q(0).LFBK AND XLXI_81/XLXN_447.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_16/Q(0).LFBK AND XLXI_81/XLXN_447.LFBK)); PORTA(0) <= PORTA_I(0) when PORTA_OE(0) = '1' else 'Z'; PORTA_OE(0) <= XLXN_144; FTCPE_PORTA1: FTCPE port map (PORTA_I(1),PORTA_T(1),DIOWn,NOT RESETn,'0'); PORTA_T(1) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_16/Q(1).LFBK AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND CSEL AND XLXI_16/Q(1).LFBK AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_16/Q(1).LFBK AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND XLXI_16/Q(1).LFBK AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK)); PORTA(1) <= PORTA_I(1) when PORTA_OE(1) = '1' else 'Z'; PORTA_OE(1) <= XLXN_144; FTCPE_PORTA2: FTCPE port map (PORTA_I(2),PORTA_T(2),DIOWn,NOT RESETn,'0'); PORTA_T(2) <= ((DD(2).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_16/Q(2).LFBK) OR (DD(2).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_16/Q(2).LFBK) OR (NOT DD(2).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_16/Q(2).LFBK) OR (NOT DD(2).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_16/Q(2).LFBK)); PORTA(2) <= PORTA_I(2) when PORTA_OE(2) = '1' else 'Z'; PORTA_OE(2) <= XLXN_144; FTCPE_PORTA3: FTCPE port map (PORTA_I(3),PORTA_T(3),DIOWn,NOT RESETn,'0'); PORTA_T(3) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_16/Q(3).LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_16/Q(3).LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_16/Q(3).LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_16/Q(3).LFBK)); PORTA(3) <= PORTA_I(3) when PORTA_OE(3) = '1' else 'Z'; PORTA_OE(3) <= XLXN_144; FTCPE_PORTA4: FTCPE port map (PORTA_I(4),PORTA_T(4),DIOWn,NOT RESETn,'0'); PORTA_T(4) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND NOT XLXI_16/Q(4).LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND NOT XLXI_16/Q(4).LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND XLXI_16/Q(4).LFBK) OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND XLXI_16/Q(4).LFBK)); PORTA(4) <= PORTA_I(4) when PORTA_OE(4) = '1' else 'Z'; PORTA_OE(4) <= XLXN_144; FTCPE_PORTA5: FTCPE port map (PORTA_I(5),PORTA_T(5),DIOWn,NOT RESETn,'0'); PORTA_T(5) <= ((DD(5).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_16/Q(5).LFBK) OR (DD(5).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_16/Q(5).LFBK) OR (NOT DD(5).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_16/Q(5).LFBK) OR (NOT DD(5).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_16/Q(5).LFBK)); PORTA(5) <= PORTA_I(5) when PORTA_OE(5) = '1' else 'Z'; PORTA_OE(5) <= XLXN_144; FTCPE_PORTA6: FTCPE port map (PORTA_I(6),PORTA_T(6),DIOWn,NOT RESETn,'0'); PORTA_T(6) <= ((DD(6).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_16/Q(6).LFBK) OR (DD(6).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_16/Q(6).LFBK) OR (NOT DD(6).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_16/Q(6).LFBK) OR (NOT DD(6).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_16/Q(6).LFBK)); PORTA(6) <= PORTA_I(6) when PORTA_OE(6) = '1' else 'Z'; PORTA_OE(6) <= XLXN_144.LFBK; FTCPE_PORTA7: FTCPE port map (PORTA_I(7),PORTA_T(7),DIOWn,NOT RESETn,'0'); PORTA_T(7) <= ((DD(7).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_16/Q(7).LFBK) OR (DD(7).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_16/Q(7).LFBK) OR (NOT DD(7).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_16/Q(7).LFBK) OR (NOT DD(7).PIN AND NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_16/Q(7).LFBK)); PORTA(7) <= PORTA_I(7) when PORTA_OE(7) = '1' else 'Z'; PORTA_OE(7) <= XLXN_144; FTCPE_PORTB0: FTCPE port map (PORTB_I(0),PORTB_T(0),DIOWn,NOT RESETn,'0'); PORTB_T(0) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK AND NOT XLXI_18/Q(0).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK AND XLXI_18/Q(0).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK AND NOT XLXI_18/Q(0).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK AND XLXI_18/Q(0).LFBK)); PORTB(0) <= PORTB_I(0) when PORTB_OE(0) = '1' else 'Z'; PORTB_OE(0) <= XLXN_146; FTCPE_PORTB1: FTCPE port map (PORTB_I(1),PORTB_T(1),DIOWn,NOT RESETn,'0'); PORTB_T(1) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(1).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK AND NOT XLXI_18/Q(1).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(1).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK AND XLXI_18/Q(1).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(1).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK AND NOT XLXI_18/Q(1).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(1).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK AND XLXI_18/Q(1).LFBK)); PORTB(1) <= PORTB_I(1) when PORTB_OE(1) = '1' else 'Z'; PORTB_OE(1) <= XLXN_146; FTCPE_PORTB2: FTCPE port map (PORTB_I(2),PORTB_T(2),DIOWn,NOT RESETn,'0'); PORTB_T(2) <= ((DD(2).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_18/Q(2).LFBK) OR (DD(2).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_18/Q(2).LFBK) OR (NOT DD(2).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_18/Q(2).LFBK) OR (NOT DD(2).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_18/Q(2).LFBK)); PORTB(2) <= PORTB_I(2) when PORTB_OE(2) = '1' else 'Z'; PORTB_OE(2) <= XLXN_146; FTCPE_PORTB3: FTCPE port map (PORTB_I(3),PORTB_T(3),DIOWn,NOT RESETn,'0'); PORTB_T(3) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_18/Q(3).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_18/Q(3).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_18/Q(3).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_18/Q(3).LFBK)); PORTB(3) <= PORTB_I(3) when PORTB_OE(3) = '1' else 'Z'; PORTB_OE(3) <= XLXN_146; FTCPE_PORTB4: FTCPE port map (PORTB_I(4),PORTB_T(4),DIOWn,NOT RESETn,'0'); PORTB_T(4) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND NOT XLXI_18/Q(4).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND NOT XLXI_18/Q(4).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND XLXI_18/Q(4).LFBK) OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND XLXI_18/Q(4).LFBK)); PORTB(4) <= PORTB_I(4) when PORTB_OE(4) = '1' else 'Z'; PORTB_OE(4) <= XLXN_146; FTCPE_PORTB5: FTCPE port map (PORTB_I(5),PORTB_T(5),DIOWn,NOT RESETn,'0'); PORTB_T(5) <= ((DD(5).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND NOT XLXI_18/Q(5).LFBK) OR (DD(5).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND NOT XLXI_18/Q(5).LFBK) OR (NOT DD(5).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND XLXI_18/Q(5).LFBK) OR (NOT DD(5).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND XLXI_18/Q(5).LFBK)); PORTB(5) <= PORTB_I(5) when PORTB_OE(5) = '1' else 'Z'; PORTB_OE(5) <= XLXN_146; FTCPE_PORTB6: FTCPE port map (PORTB_I(6),PORTB_T(6),DIOWn,NOT RESETn,'0'); PORTB_T(6) <= ((DD(6).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_18/Q(6).LFBK) OR (DD(6).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_18/Q(6).LFBK) OR (NOT DD(6).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_18/Q(6).LFBK) OR (NOT DD(6).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_18/Q(6).LFBK)); PORTB(6) <= PORTB_I(6) when PORTB_OE(6) = '1' else 'Z'; PORTB_OE(6) <= XLXN_146.LFBK; FTCPE_PORTB7: FTCPE port map (PORTB_I(7),PORTB_T(7),DIOWn,NOT RESETn,'0'); PORTB_T(7) <= ((DD(7).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_18/Q(7).LFBK) OR (DD(7).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_18/Q(7).LFBK) OR (NOT DD(7).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_18/Q(7).LFBK) OR (NOT DD(7).PIN AND DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_18/Q(7).LFBK)); PORTB(7) <= PORTB_I(7) when PORTB_OE(7) = '1' else 'Z'; PORTB_OE(7) <= XLXN_146.LFBK; FTCPE_PORTC0: FTCPE port map (PORTC_I(0),PORTC_T(0),DIOWn,NOT RESETn,'0'); PORTC_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK AND NOT XLXI_19/Q(0).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_447.LFBK AND XLXI_19/Q(0).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK AND NOT XLXI_19/Q(0).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_81/XLXN_447.LFBK AND XLXI_19/Q(0).LFBK)); PORTC(0) <= PORTC_I(0) when PORTC_OE(0) = '1' else 'Z'; PORTC_OE(0) <= XLXN_147; FTCPE_PORTC1: FTCPE port map (PORTC_I(1),PORTC_T(1),DIOWn,NOT RESETn,'0'); PORTC_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_19/Q(1).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_19/Q(1).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_19/Q(1).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_19/Q(1).LFBK)); PORTC(1) <= PORTC_I(1) when PORTC_OE(1) = '1' else 'Z'; PORTC_OE(1) <= XLXN_147; FTCPE_PORTC2: FTCPE port map (PORTC_I(2),PORTC_T(2),DIOWn,NOT RESETn,'0'); PORTC_T(2) <= ((DD(2).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_19/Q(2).LFBK) OR (DD(2).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND NOT XLXI_19/Q(2).LFBK) OR (NOT DD(2).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_19/Q(2).LFBK) OR (NOT DD(2).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_449.LFBK AND XLXI_19/Q(2).LFBK)); PORTC(2) <= PORTC_I(2) when PORTC_OE(2) = '1' else 'Z'; PORTC_OE(2) <= XLXN_147; FTCPE_PORTC3: FTCPE port map (PORTC_I(3),PORTC_T(3),DIOWn,NOT RESETn,'0'); PORTC_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_19/Q(3).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_19/Q(3).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND NOT XLXI_19/Q(3).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND NOT CSEL AND NOT XLXI_81/XLXN_448.LFBK AND XLXI_81/XLXN_450.LFBK AND XLXI_19/Q(3).LFBK)); PORTC(3) <= PORTC_I(3) when PORTC_OE(3) = '1' else 'Z'; PORTC_OE(3) <= XLXN_147; FTCPE_PORTC4: FTCPE port map (PORTC_I(4),PORTC_T(4),DIOWn,NOT RESETn,'0'); PORTC_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND NOT XLXI_19/Q(4).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND NOT XLXI_19/Q(4).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_81/XLXN_43.LFBK AND XLXI_19/Q(4).LFBK) OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_81/XLXN_43.LFBK AND XLXI_19/Q(4).LFBK)); PORTC(4) <= PORTC_I(4) when PORTC_OE(4) = '1' else 'Z'; PORTC_OE(4) <= XLXN_145; FTCPE_PORTC5: FTCPE port map (PORTC_I(5),PORTC_T(5),DIOWn,NOT RESETn,'0'); PORTC_T(5) <= ((DD(5).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_19/Q(5).LFBK) OR (DD(5).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_19/Q(5).LFBK) OR (NOT DD(5).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_19/Q(5).LFBK) OR (NOT DD(5).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_19/Q(5).LFBK)); PORTC(5) <= PORTC_I(5) when PORTC_OE(5) = '1' else 'Z'; PORTC_OE(5) <= XLXN_145; FTCPE_PORTC6: FTCPE port map (PORTC_I(6),PORTC_T(6),DIOWn,NOT RESETn,'0'); PORTC_T(6) <= ((DD(6).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_19/Q(6).LFBK) OR (DD(6).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_19/Q(6).LFBK) OR (NOT DD(6).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_19/Q(6).LFBK) OR (NOT DD(6).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_19/Q(6).LFBK)); PORTC(6) <= PORTC_I(6) when PORTC_OE(6) = '1' else 'Z'; PORTC_OE(6) <= XLXN_145.LFBK; FTCPE_PORTC7: FTCPE port map (PORTC_I(7),PORTC_T(7),DIOWn,NOT RESETn,'0'); PORTC_T(7) <= ((DD(7).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXI_19/Q(7).LFBK) OR (DD(7).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_19/Q(7).LFBK) OR (NOT DD(7).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXI_19/Q(7).LFBK) OR (NOT DD(7).PIN AND NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXI_19/Q(7).LFBK)); PORTC(7) <= PORTC_I(7) when PORTC_OE(7) = '1' else 'Z'; PORTC_OE(7) <= XLXN_145; REO <= ((XLXN_147.EXP) OR (NOT DIORn AND DA0 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DIORn AND DA0 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL) OR (NOT DIORn AND NOT DA1 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL) OR (NOT DIORn AND NOT DA1 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL) OR (NOT DIORn AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL)); SELECTEDn <= XLXI_81/XLXN_43 XOR SELECTEDn <= CSEL; FTCPE_XLXI_81/XLXN_43: FTCPE port map (XLXI_81/XLXN_43,XLXI_81/XLXN_43_T,DIOWn,NOT RESETn,'0'); XLXI_81/XLXN_43_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND DD(4).PIN AND NOT XLXI_81/XLXN_43.LFBK) OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DD(4).PIN AND XLXI_81/XLXN_43.LFBK)); FTCPE_XLXN_144: FTCPE port map (XLXN_144,XLXN_144_T,DIOWn,NOT RESETn,'0'); XLXN_144_T <= ((NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXN_144.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXN_144.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXN_144.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXN_144.LFBK)); FTCPE_XLXN_145: FTCPE port map (XLXN_145,XLXN_145_T,DIOWn,NOT RESETn,'0'); XLXN_145_T <= ((NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXN_145.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXN_145.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXN_145.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXN_145.LFBK)); FTCPE_XLXN_146: FTCPE port map (XLXN_146,XLXN_146_T,DIOWn,NOT RESETn,'0'); XLXN_146_T <= ((NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXN_146.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXN_146.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXN_146.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXN_146.LFBK)); FTCPE_XLXN_147: FTCPE port map (XLXN_147,XLXN_147_T,DIOWn,NOT RESETn,'0'); XLXN_147_T <= ((NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND DD(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND XLXN_147.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND XLXI_81/XLXN_43 AND NOT DD(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND CSEL AND NOT XLXN_147.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND DD(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND XLXN_147.LFBK) OR (NOT DD(2).PIN AND DD(7).PIN AND NOT DD(6).PIN AND NOT DD(5).PIN AND DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT XLXI_81/XLXN_43 AND NOT DD(0).PIN AND DH0n AND NOT DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXN_147.LFBK)); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-7-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-7-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 PGND 43 DH3n 2 PGND 44 DA0 3 PORTB<0> 45 PORTA<7> 4 PORTB<1> 46 PGND 5 PORTA<0> 47 PGND 6 PGND 48 PORTC<5> 7 PORTC<0> 49 GND 8 GND 50 PORTC<7> 9 DIORn 51 DD<0> 10 DIOWn 52 DD<2> 11 DD<5> 53 SELECTEDn 12 PGND 54 CS0n 13 DH0n 55 DMARQ 14 PGND 56 DMACKn 15 PGND 57 PGND 16 GND 58 PGND 17 PORTB<4> 59 TDO 18 PORTB<5> 60 GND 19 PORTA<4> 61 PORTB<6> 20 PGND 62 PORTB<7> 21 PORTC<4> 63 PORTA<6> 22 VCC 64 VCC 23 DD<1> 65 PGND 24 DD<7> 66 PORTC<6> 25 PGND 67 DD<3> 26 DA2 68 REO 27 GND 69 CS1n 28 TDI 70 DA1 29 TMS 71 PGND 30 TCK 72 PGND 31 CSEL 73 VCC 32 PORTA<1> 74 RESETn 33 PORTA<3> 75 PORTB<2> 34 PORTA<5> 76 REI 35 PGND 77 PGND 36 PGND 78 VCC 37 PORTC<1> 79 PORTB<3> 38 VCC 80 PORTA<2> 39 PORTC<3> 81 PGND 40 DD<6> 82 PORTC<2> 41 DH1n 83 DD<4> 42 GND 84 DH2n Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-7-PC84 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : STD Ground on Unused IOs : ON Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25