cpldfit:  version I.27                              Xilinx Inc.
                                  Fitter Report
Design Name: ata_to_isa_06c                      Date: 10- 8-2006, 12:31PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
94 /108 ( 87%) 410 /540  ( 76%) 215/216 ( 99%)   73 /108 ( 68%) 61 /69  ( 88%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          18/18*      36/36*      44          52/90       7/12
FB2          16/18       36/36*      40          54/90       7/12
FB3          12/18       36/36*      46          78/90       9/12
FB4          18/18*      36/36*      40          83/90       7/11
FB5          12/18       36/36*      44          66/90       7/11
FB6          18/18*      35/36       35          77/90       7/11
             -----       -----                   -----       -----     
             94/108     215/216                 410/540     44/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'DIOWn' mapped onto global clock net GCK1.
The complement of 'DIORn' mapped onto global clock net GCK2.
Signal 'REI' mapped onto global output enable net GTS1.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   14          14    |  I/O              :    58      63
Output        :   28          28    |  GCK/IO           :     2       3
Bidirectional :   16          16    |  GTS/IO           :     1       2
GCK           :    2           2    |  GSR/IO           :     0       1
GTS           :    1           1    |
GSR           :    0           0    |
                 ----        ----
        Total     61          61

** Power Data **

There are 94 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 44 Outputs **

Signal                        Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                          Pts   Inps          No.  Type    Use     Mode Rate State
SD<4>                         6     18    FB1_2   1    I/O     I/O     STD  SLOW RESET
IOWn                          1     2     FB1_3   2    I/O     O       STD  SLOW 
SD<5>                         6     18    FB1_5   3    I/O     I/O     STD  SLOW RESET
SD<6>                         6     18    FB1_8   5    I/O     I/O     STD  SLOW RESET
AEN                           5     17    FB1_11  7    I/O     O       STD  SLOW SET
IORDY                         3     15    FB1_15  11   I/O     O       STD  SLOW 
SELECTEDn                     2     2     FB1_17  13   I/O     O       STD  SLOW 
SA_LOW<0>                     5     17    FB2_2   71   I/O     O       STD  SLOW RESET
SA_LOW<1>                     5     17    FB2_3   72   I/O     O       STD  SLOW RESET
SA_LOW<2>                     5     17    FB2_6   75   I/O     O       STD  SLOW RESET
SA_LOW<7>                     5     17    FB2_11  79   I/O     O       STD  SLOW RESET
SA_HIGH<0>                    5     17    FB2_12  80   I/O     O       STD  SLOW RESET
SA_HIGH<1>                    5     17    FB2_15  82   I/O     O       STD  SLOW RESET
SA_HIGH<7>                    5     17    FB2_17  84   I/O     O       STD  SLOW RESET
DD<2>                         12    16    FB3_2   14   I/O     I/O     STD  SLOW 
INTRQ                         2     6     FB3_3   15   I/O     O       STD  SLOW 
DD<3>                         12    16    FB3_5   17   I/O     I/O     STD  SLOW 
DD<5>                         12    16    FB3_8   19   I/O     I/O     STD  SLOW 
ISA_RESET                     1     2     FB3_9   20   I/O     O       STD  SLOW 
DD<6>                         12    16    FB3_11  21   I/O     I/O     STD  SLOW 
DD<7>                         12    16    FB3_14  24   I/O     I/O     STD  SLOW 
IORn                          1     2     FB3_16  26   I/O     O       STD  SLOW 
SEQn                          4     6     FB3_17  31   I/O     O       STD  SLOW SET
SA_LOW<4>                     5     17    FB4_2   57   I/O     O       STD  SLOW RESET
SA_HIGH<6>                    5     17    FB4_3   58   I/O     O       STD  SLOW RESET
SA_LOW<5>                     5     17    FB4_6   62   I/O     O       STD  SLOW RESET
SA_LOW<6>                     5     17    FB4_8   63   I/O     O       STD  SLOW RESET
SA_HIGH<3>                    5     17    FB4_11  66   I/O     O       STD  SLOW RESET
SA_HIGH<4>                    5     17    FB4_14  68   I/O     O       STD  SLOW RESET
SA_HIGH<5>                    5     17    FB4_17  70   I/O     O       STD  SLOW RESET
ISA_READn                     5     7     FB5_2   32   I/O     O       STD  SLOW SET
ITRPn                         1     5     FB5_3   33   I/O     O       STD  SLOW 
DD<1>                         12    16    FB5_5   34   I/O     I/O     STD  SLOW 
SD<3>                         6     18    FB5_8   36   I/O     I/O     STD  SLOW RESET
DD<4>                         12    16    FB5_11  39   I/O     I/O     STD  SLOW 
ISA_WRITEn                    5     6     FB5_14  41   I/O     O       STD  SLOW SET
DD<0>                         12    16    FB5_17  44   I/O     I/O     STD  SLOW 
SD<0>                         6     17    FB6_2   45   I/O     I/O     STD  SLOW RESET
SA_HIGH<2>                    5     16    FB6_3   46   I/O     O       STD  SLOW RESET
SD<1>                         6     17    FB6_6   48   I/O     I/O     STD  SLOW RESET

Signal                        Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                          Pts   Inps          No.  Type    Use     Mode Rate State
SD<2>                         6     17    FB6_8   50   I/O     I/O     STD  SLOW RESET
SD<7>                         6     17    FB6_11  52   I/O     I/O     STD  SLOW RESET
REO                           6     14    FB6_14  54   I/O     O       STD  SLOW 
SA_LOW<3>                     5     16    FB6_17  56   I/O     O       STD  SLOW RESET

** 50 Buried Nodes **

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
XLXN_803<6>                   0     0     FB1_1   STD  RESET
XLXN_803<5>                   0     0     FB1_4   STD  RESET
XLXN_803<4>                   0     0     FB1_6   STD  RESET
$OpTx$$OpTx$FX_DC$20_INV$52   1     3     FB1_7   STD  
$OpTx$FX_DC$18                2     2     FB1_9   STD  
XLXN_802<7>                   3     4     FB1_10  STD  RESET
XLXN_802<2>                   3     4     FB1_12  STD  RESET
XLXN_802<1>                   3     4     FB1_13  STD  RESET
XLXI_620/XLXN_43              3     10    FB1_14  STD  RESET
RD_REQUEST                    3     3     FB1_16  STD  RESET
GATE_IORDY                    5     17    FB1_18  STD  RESET
XLXN_803<3>                   1     1     FB2_5   STD  RESET
XLXN_803<2>                   1     1     FB2_7   STD  RESET
XLXN_803<1>                   1     1     FB2_8   STD  RESET
XLXN_428/XLXN_428_SETF__$INT  1     2     FB2_9   STD  
ITRP_STA<3>                   2     4     FB2_10  STD  RESET
ITRP_STA<2>                   2     4     FB2_13  STD  RESET
XLXN_802<3>                   3     4     FB2_14  STD  RESET
WR_PENDING                    3     15    FB2_16  STD  RESET
INTE_D                        5     17    FB2_18  STD  RESET
XLXN_802<0>                   3     4     FB3_4   STD  RESET
WR_REQUEST                    3     3     FB3_15  STD  RESET
ISA_PULSE                     4     8     FB3_18  STD  RESET
WR_PENDING/WR_PENDING_RSTF    3     5     FB4_1   STD  
RD_PENDING/RD_PENDING_RSTF    3     5     FB4_4   STD  
RD_PENDING                    3     15    FB4_5   STD  RESET
QSR<7>                        4     6     FB4_7   STD  RESET
XLXI_385/Q<4>                 5     7     FB4_9   STD  RESET
XLXI_385/Q<3>                 5     7     FB4_10  STD  RESET
RESET_CTL                     5     17    FB4_12  STD  RESET
QSR<6>                        5     7     FB4_13  STD  RESET
QSR<5>                        5     7     FB4_15  STD  RESET
QSR<2>                        5     7     FB4_16  STD  RESET
QSR<1>                        5     7     FB4_18  STD  RESET
XLXN_802<5>                   3     4     FB5_1   STD  RESET
XLXN_803<7>                   0     0     FB5_12  STD  RESET
XLXN_802<6>                   3     4     FB5_13  STD  RESET
XLXN_802<4>                   3     4     FB5_15  STD  RESET
WR_DATA_ENABLE                4     6     FB5_18  STD  RESET
XLXN_803<0>                   1     1     FB6_1   STD  RESET

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
ITRP_STA<1>                   2     4     FB6_4   STD  RESET
ITRP_STA<0>                   2     4     FB6_5   STD  RESET
DH3                           3     10    FB6_7   STD  RESET
DH2                           3     10    FB6_9   STD  RESET
DH1                           3     10    FB6_10  STD  RESET
DH0                           3     10    FB6_12  STD  RESET
INTE_C                        5     16    FB6_13  STD  RESET
INTE_B                        5     16    FB6_15  STD  RESET
INTE_A                        5     16    FB6_16  STD  RESET
GATE_ITRP                     5     16    FB6_18  STD  RESET

** 17 Inputs **

Signal                        Loc     Pin  Pin     Pin     
Name                                  No.  Type    Use     
CSEL                          FB1_6   4    I/O     I
INT_D                         FB1_9   6    I/O     I
DIOWn                         FB1_12  9    GCK/I/O GCK/I
DIORn                         FB1_14  10   GCK/I/O GCK/I
REI                           FB2_8   76   GTS/I/O GTS
DMARQ                         FB2_14  81   I/O     I
DA0                           FB2_16  83   I/O     I
INT_A                         FB3_6   18   I/O     I
DMACKn                        FB4_9   65   I/O     I
INT_C                         FB4_12  67   I/O     I
CS0n                          FB4_15  69   I/O     I
DA2                           FB5_9   37   I/O     I
INT_B                         FB5_12  40   I/O     I
CLK                           FB5_15  43   I/O     I
CS1n                          FB6_5   47   I/O     I
DA1                           FB6_12  53   I/O     I
RESETn                        FB6_15  55   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXN_803<6>           0       0   \/1   4     FB1_1         (b)     (b)
SD<4>                 6       1<-   0   0     FB1_2   1     I/O     I/O
IOWn                  1       0     0   4     FB1_3   2     I/O     O
XLXN_803<5>           0       0   \/1   4     FB1_4         (b)     (b)
SD<5>                 6       1<-   0   0     FB1_5   3     I/O     I/O
XLXN_803<4>           0       0     0   5     FB1_6   4     I/O     I
$OpTx$$OpTx$FX_DC$20_INV$52
                      1       0   \/1   3     FB1_7         (b)     (b)
SD<6>                 6       1<-   0   0     FB1_8   5     I/O     I/O
$OpTx$FX_DC$18        2       0     0   3     FB1_9   6     I/O     I
XLXN_802<7>           3       0     0   2     FB1_10        (b)     (b)
AEN                   5       0     0   0     FB1_11  7     I/O     O
XLXN_802<2>           3       0     0   2     FB1_12  9     GCK/I/O GCK/I
XLXN_802<1>           3       0     0   2     FB1_13        (b)     (b)
XLXI_620/XLXN_43      3       0     0   2     FB1_14  10    GCK/I/O GCK/I
IORDY                 3       0     0   2     FB1_15  11    I/O     O
RD_REQUEST            3       0     0   2     FB1_16  12    GCK/I/O (b)
SELECTEDn             2       0     0   3     FB1_17  13    I/O     O
GATE_IORDY            5       0     0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$20_INV$52  16: ISA_WRITEn           31: DIORn 
  2: $OpTx$FX_DC$18               17: ISA_WR_DATA<4>.LFBK  32: CSEL 
  3: DA0                          18: ISA_WR_DATA<5>.LFBK  33: DMARQ 
  4: DA1                          19: ISA_WR_DATA<6>.LFBK  34: CS0n 
  5: DA2                          20: QSR<5>               35: XLXI_620/XLXN_43.LFBK 
  6: DH0                          21: SD<1>.PIN            36: RESETn 
  7: DH1                          22: SD<2>.PIN            37: DMACKn 
  8: DH2                          23: SD<7>.PIN            38: CS1n 
  9: DH3                          24: RD_PENDING           39: XLXN_413.LFBK 
 10: FC_0_.OUT                    25: WR_DATA_ENABLE       40: XLXN_428/XLXN_428_SETF__$INT 
 11: FC_1_.OUT                    26: WR_PENDING           41: XLXN_802<1>.LFBK 
 12: FC_2_.OUT                    27: DIOWn                42: XLXN_802<2>.LFBK 
 13: GATE_IORDY.LFBK              28: DD<4>.PIN            43: XLXN_802<7>.LFBK 
 14: ISA_PULSE                    29: DD<5>.PIN            44: CLK 
 15: ISA_READn                    30: DD<6>.PIN           

Signal                        1         2         3         4         5 Signals FB
Name                0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
XLXN_803<6>          .................................................. 0       0
SD<4>                ..XXX@@@@X......X.......X..X...XXXXXXX............ 18      14
IOWn                 .............X.X.................................. 2       2
XLXN_803<5>          .................................................. 0       0
SD<5>                ..XXX@@@@X.......X......X...X..XXXXXXX............ 18      14
XLXN_803<4>          .................................................. 0       0
$OpTx$$OpTx$FX_DC$20_INV$52 
                     ..XXX............................................. 3       3
SD<6>                ..XXX@@@@X........X.....X....X.XXXXXXX............ 18      14
$OpTx$FX_DC$18       ...............................X..X............... 2       2
XLXN_802<7>          ...................X..X...................XX...... 4       4
AEN                  ..XXX@@@@X...................X.XXXXXXXX........... 17      13
XLXN_802<2>          ...................X.X...................X.X...... 4       4
XLXN_802<1>          ...................XX...................X..X...... 4       4
XLXI_620/XLXN_43     ..XXX......................X....XXXXXX............ 10      10
IORDY                @@........XXX.@X.......X.@X...X.XX..XX............ 15      11
RD_REQUEST           .......................X...............X...X...... 3       3
SELECTEDn            ...............................X..X............... 2       2
GATE_IORDY           ..XXX@@@@X..X...............X..XXXXXXX............ 17      13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  40
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
SA_LOW<0>             5       0     0   0     FB2_2   71    I/O     O
SA_LOW<1>             5       0     0   0     FB2_3   72    I/O     O
(unused)              0       0     0   5     FB2_4         (b)     
XLXN_803<3>           1       0     0   4     FB2_5   74    GSR/I/O (b)
SA_LOW<2>             5       0     0   0     FB2_6   75    I/O     O
XLXN_803<2>           1       0     0   4     FB2_7         (b)     (b)
XLXN_803<1>           1       0     0   4     FB2_8   76    GTS/I/O GTS
XLXN_428/XLXN_428_SETF__$INT
                      1       0     0   4     FB2_9   77    GTS/I/O (b)
ITRP_STA<3>           2       0     0   3     FB2_10        (b)     (b)
SA_LOW<7>             5       0     0   0     FB2_11  79    I/O     O
SA_HIGH<0>            5       0     0   0     FB2_12  80    I/O     O
ITRP_STA<2>           2       0     0   3     FB2_13        (b)     (b)
XLXN_802<3>           3       0     0   2     FB2_14  81    I/O     I
SA_HIGH<1>            5       0     0   0     FB2_15  82    I/O     O
WR_PENDING            3       0     0   2     FB2_16  83    I/O     I
SA_HIGH<7>            5       0     0   0     FB2_17  84    I/O     O
INTE_D                5       0     0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0               15: SD<3>.PIN                   28: DMACKn 
  2: DA1               16: RESET_CTL                   29: CS1n 
  3: DA2               17: WR_PENDING/WR_PENDING_RSTF  30: INT_C 
  4: DH0               18: DD<0>.PIN                   31: INT_D 
  5: DH1               19: DD<1>.PIN                   32: XLXN_48<0>.LFBK 
  6: DH2               20: DD<2>.PIN                   33: XLXN_48<1>.LFBK 
  7: DH3               21: DD<3>.PIN                   34: XLXN_48<2>.LFBK 
  8: FC_0_.OUT         22: DD<7>.PIN                   35: XLXN_48<7>.LFBK 
  9: INTE_C            23: CSEL                        36: XLXN_49<0>.LFBK 
 10: INTE_D.LFBK       24: DMARQ                       37: XLXN_49<1>.LFBK 
 11: ITRP_STA<1>       25: CS0n                        38: XLXN_49<7>.LFBK 
 12: ITRP_STA<2>.LFBK  26: XLXI_620/XLXN_43            39: XLXN_802<3>.LFBK 
 13: ITRP_STA<3>.LFBK  27: RESETn                      40: CLK 
 14: QSR<5>           

Signal                        1         2         3         4         5 Signals FB
Name                0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
SA_LOW<0>            XXX@@@@X.........X....XXXXXXX..X.................. 17      13
SA_LOW<1>            XXX@@@@X..........X...XXXXXXX...X................. 17      13
XLXN_803<3>          ............X..................................... 1       1
SA_LOW<2>            XXX@@@@X...........X..XXXXXXX....X................ 17      13
XLXN_803<2>          ...........X...................................... 1       1
XLXN_803<1>          ..........X....................................... 1       1
XLXN_428/XLXN_428_SETF__$INT 
                     ...............X..........X....................... 2       2
ITRP_STA<3>          .........X.....X..........X...X................... 4       4
SA_LOW<7>            XXX@@@@X.............XXXXXXXX.....X............... 17      13
SA_HIGH<0>           XXX@@@@X.........X....XXXXXXX......X.............. 17      13
ITRP_STA<2>          ........X......X..........X..X.................... 4       4
XLXN_802<3>          .............XX.......................XX.......... 4       4
SA_HIGH<1>           XXX@@@@X..........X...XXXXXXX.......X............. 17      13
WR_PENDING           XXX@@@@X........X.....XXXX.XX..................... 15      11
SA_HIGH<7>           XXX@@@@X.............XXXXXXXX........X............ 17      13
INTE_D               XXX@@@@X.X..........X.XXXXXXX..................... 17      13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  46
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB3_1         (b)     (b)
DD<2>                12       7<-   0   0     FB3_2   14    I/O     I/O
INTRQ                 2       0   /\2   1     FB3_3   15    I/O     O
XLXN_802<0>           3       0   \/2   0     FB3_4         (b)     (b)
DD<3>                12       7<-   0   0     FB3_5   17    I/O     I/O
(unused)              0       0   /\5   0     FB3_6   18    I/O     I
(unused)              0       0   \/5   0     FB3_7         (b)     (b)
DD<5>                12       7<-   0   0     FB3_8   19    I/O     I/O
ISA_RESET             1       0   /\2   2     FB3_9   20    I/O     O
(unused)              0       0   \/5   0     FB3_10        (b)     (b)
DD<6>                12       7<-   0   0     FB3_11  21    I/O     I/O
(unused)              0       0   /\2   3     FB3_12  23    I/O     (b)
(unused)              0       0   \/5   0     FB3_13        (b)     (b)
DD<7>                12       7<-   0   0     FB3_14  24    I/O     I/O
WR_REQUEST            3       0   /\2   0     FB3_15  25    I/O     (b)
IORn                  1       0     0   4     FB3_16  26    I/O     O
SEQn                  4       0     0   1     FB3_17  31    I/O     O
ISA_PULSE             4       0     0   1     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0               17: ITRP_STA<1>       32: DMACKn 
  2: DA1               18: ITRP_STA<2>       33: CS1n 
  3: DA2               19: ITRP_STA<3>       34: XLXN_428/XLXN_428_SETF__$INT 
  4: DH0               20: QSR<5>            35: XLXN_802<0>.LFBK 
  5: DH1               21: QSR<7>            36: XLXN_802<2> 
  6: DH2               22: SD<0>.PIN         37: XLXN_802<3> 
  7: DH3               23: RD_REQUEST        38: XLXN_802<5> 
  8: FC_0_.OUT         24: RESET_CTL         39: XLXN_802<6> 
  9: FC_3_.OUT         25: WR_PENDING        40: XLXN_802<7> 
 10: FC_4_.OUT         26: WR_REQUEST        41: XLXN_803<2> 
 11: GATE_ITRP         27: CSEL              42: XLXN_803<3> 
 12: IDLE.LFBK         28: DMARQ             43: XLXN_803<5> 
 13: ISA_PULSE.LFBK    29: CS0n              44: XLXN_803<6> 
 14: ISA_READn         30: XLXI_620/XLXN_43  45: XLXN_803<7> 
 15: ISA_WRITEn        31: RESETn            46: CLK 
 16: ITRP_STA<0>      

Signal                        1         2         3         4         5 Signals FB
Name                0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
DD<2>                XXXXXXXX..................XXXX.XX..X....X......... 16      16
INTRQ                ........X.X....@@@@............................... 6       2
XLXN_802<0>          ...................X.X............X..........X.... 4       4
DD<3>                XXXXXXXX..................XXXX.XX...X....X........ 16      16
DD<5>                XXXXXXXX..................XXXX.XX....X....X....... 16      16
ISA_RESET            .......................X......X................... 2       2
DD<6>                XXXXXXXX..................XXXX.XX.....X....X...... 16      16
DD<7>                XXXXXXXX..................XXXX.XX......X....X..... 16      16
WR_REQUEST           ........................X........X...........X.... 3       3
IORn                 ............XX.................................... 2       2
SEQn                 ...........X.XX.....X............X...........X.... 6       6
ISA_PULSE            .........X.XX......X..@..@.......X...........X.... 8       6
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  40
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
WR_PENDING/WR_PENDING_RSTF
                      3       0     0   2     FB4_1         (b)     (b)
SA_LOW<4>             5       0     0   0     FB4_2   57    I/O     O
SA_HIGH<6>            5       0     0   0     FB4_3   58    I/O     O
RD_PENDING/RD_PENDING_RSTF
                      3       0     0   2     FB4_4         (b)     (b)
RD_PENDING            3       0     0   2     FB4_5   61    I/O     (b)
SA_LOW<5>             5       0     0   0     FB4_6   62    I/O     O
QSR<7>                4       0     0   1     FB4_7         (b)     (b)
SA_LOW<6>             5       0     0   0     FB4_8   63    I/O     O
XLXI_385/Q<4>         5       0     0   0     FB4_9   65    I/O     I
XLXI_385/Q<3>         5       0     0   0     FB4_10        (b)     (b)
SA_HIGH<3>            5       0     0   0     FB4_11  66    I/O     O
RESET_CTL             5       0     0   0     FB4_12  67    I/O     I
QSR<6>                5       0     0   0     FB4_13        (b)     (b)
SA_HIGH<4>            5       0     0   0     FB4_14  68    I/O     O
QSR<5>                5       0     0   0     FB4_15  69    I/O     I
QSR<2>                5       0     0   0     FB4_16        (b)     (b)
SA_HIGH<5>            5       0     0   0     FB4_17  70    I/O     O
QSR<1>                5       0     0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0               15: QSR<7>.LFBK                      28: XLXI_620/XLXN_43 
  2: DA1               16: RD_PENDING/RD_PENDING_RSTF.LFBK  29: RESETn 
  3: DA2               17: RESET_CTL.LFBK                   30: DMACKn 
  4: DH0               18: SEQn                             31: CS1n 
  5: DH1               19: DD<3>.PIN                        32: XLXN_428/XLXN_428_SETF__$INT 
  6: DH2               20: DD<4>.PIN                        33: XLXN_48<4>.LFBK 
  7: DH3               21: DD<5>.PIN                        34: XLXN_48<5>.LFBK 
  8: FC_0_.OUT         22: DD<6>.PIN                        35: XLXN_48<6>.LFBK 
  9: ISA_READn         23: XLXI_385/Q<3>.LFBK               36: XLXN_49<3>.LFBK 
 10: ISA_WRITEn        24: XLXI_385/Q<4>.LFBK               37: XLXN_49<4>.LFBK 
 11: QSR<1>.LFBK       25: CSEL                             38: XLXN_49<5>.LFBK 
 12: QSR<2>.LFBK       26: DMARQ                            39: XLXN_49<6>.LFBK 
 13: QSR<5>.LFBK       27: CS0n                             40: CLK 
 14: QSR<6>.LFBK      

Signal                        1         2         3         4         5 Signals FB
Name                0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
WR_PENDING/WR_PENDING_RSTF 
                     .........XXX....X...........X..................... 5       5
SA_LOW<4>            XXX@@@@X...........X....XXXXXXX.X................. 17      13
SA_HIGH<6>           XXX@@@@X.............X..XXXXXXX.......X........... 17      13
RD_PENDING/RD_PENDING_RSTF 
                     ........X.XX....X...........X..................... 5       5
RD_PENDING           XXX@@@@X.......X........XXXX.XX................... 15      11
SA_LOW<5>            XXX@@@@X............X...XXXXXXX..X................ 17      13
QSR<7>               ........XX...XX................X.......X.......... 6       6
SA_LOW<6>            XXX@@@@X.............X..XXXXXXX...X............... 17      13
XLXI_385/Q<4>        ........XX....X.......XX.......X.......X.......... 7       7
XLXI_385/Q<3>        ........XX.X..X.......X........X.......X.......... 7       7
SA_HIGH<3>           XXX@@@@X..........X.....XXXXXXX....X.............. 17      13
RESET_CTL            XXX@@@@X........X..X....XXXXXXX................... 17      13
QSR<6>               ........XX..XXX................X.......X.......... 7       7
SA_HIGH<4>           XXX@@@@X...........X....XXXXXXX.....X............. 17      13
QSR<5>               ........XX..X.X........X.......X.......X.......... 7       7
QSR<2>               ........XXXX..X................X.......X.......... 7       7
SA_HIGH<5>           XXX@@@@X............X...XXXXXXX......X............ 17      13
QSR<1>               ........XXX...X..X.............X.......X.......... 7       7
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXN_802<5>           3       0     0   2     FB5_1         (b)     (b)
ISA_READn             5       0     0   0     FB5_2   32    I/O     O
ITRPn                 1       0     0   4     FB5_3   33    I/O     O
(unused)              0       0   \/4   1     FB5_4         (b)     (b)
DD<1>                12       7<-   0   0     FB5_5   34    I/O     I/O
(unused)              0       0   /\3   2     FB5_6   35    I/O     (b)
(unused)              0       0   \/1   4     FB5_7         (b)     (b)
SD<3>                 6       1<-   0   0     FB5_8   36    I/O     I/O
(unused)              0       0     0   5     FB5_9   37    I/O     I
(unused)              0       0   \/5   0     FB5_10        (b)     (b)
DD<4>                12       7<-   0   0     FB5_11  39    I/O     I/O
XLXN_803<7>           0       0   /\2   3     FB5_12  40    I/O     I
XLXN_802<6>           3       0     0   2     FB5_13        (b)     (b)
ISA_WRITEn            5       0     0   0     FB5_14  41    I/O     O
XLXN_802<4>           3       0   \/1   1     FB5_15  43    I/O     I
(unused)              0       0   \/5   0     FB5_16        (b)     (b)
DD<0>                12       7<-   0   0     FB5_17  44    I/O     I/O
WR_DATA_ENABLE        4       0   /\1   0     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0                  16: QSR<6>               31: DMACKn 
  2: DA1                  17: QSR<7>               32: CS1n 
  3: DA2                  18: SD<4>.PIN            33: XLXN_425.LFBK 
  4: DH0                  19: SD<5>.PIN            34: XLXN_428.LFBK 
  5: DH1                  20: SD<6>.PIN            35: XLXN_428/XLXN_428_SETF__$INT 
  6: DH2                  21: RD_REQUEST           36: XLXN_802<0> 
  7: DH3                  22: SEQn                 37: XLXN_802<1> 
  8: FC_0_.OUT            23: WR_DATA_ENABLE.LFBK  38: XLXN_802<4>.LFBK 
  9: FC_3_.OUT            24: WR_REQUEST           39: XLXN_802<5>.LFBK 
 10: ISA_WR_DATA<3>.LFBK  25: DD<3>.PIN            40: XLXN_802<6>.LFBK 
 11: ITRP_STA<0>          26: CSEL                 41: XLXN_803<0> 
 12: ITRP_STA<1>          27: DMARQ                42: XLXN_803<1> 
 13: ITRP_STA<2>          28: CS0n                 43: XLXN_803<4> 
 14: ITRP_STA<3>          29: XLXI_620/XLXN_43     44: CLK 
 15: QSR<5>               30: RESETn              

Signal                        1         2         3         4         5 Signals FB
Name                0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
XLXN_802<5>          ..............X...X...................X....X...... 4       4
ISA_READn            ................X...XX.X.........XX........X...... 7       7
ITRPn                ........X.@@@@.................................... 5       1
DD<1>                XXXXXXXX.................XXXX.XX....X....X........ 16      16
SD<3>                XXX@@@@X.X............X.XXXXXXXX.................. 18      14
DD<4>                XXXXXXXX.................XXXX.XX.....X....X....... 16      16
XLXN_803<7>          .................................................. 0       0
XLXN_802<6>          ..............X....X...................X...X...... 4       4
ISA_WRITEn           ................X....X.X........X.X........X...... 6       6
XLXN_802<4>          ..............X..X...................X.....X...... 4       4
DD<0>                XXXXXXXX.................XXXX.XX...X....X......... 16      16
WR_DATA_ENABLE       ...............X.....XXX..........X........X...... 6       6
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               35/1
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXN_803<0>           1       0   \/1   3     FB6_1         (b)     (b)
SD<0>                 6       1<-   0   0     FB6_2   45    I/O     I/O
SA_HIGH<2>            5       0     0   0     FB6_3   46    I/O     O
ITRP_STA<1>           2       0     0   3     FB6_4         (b)     (b)
ITRP_STA<0>           2       0   \/1   2     FB6_5   47    I/O     I
SD<1>                 6       1<-   0   0     FB6_6   48    I/O     I/O
DH3                   3       0   \/1   1     FB6_7         (b)     (b)
SD<2>                 6       1<-   0   0     FB6_8   50    I/O     I/O
DH2                   3       0     0   2     FB6_9   51    I/O     (b)
DH1                   3       0   \/1   1     FB6_10        (b)     (b)
SD<7>                 6       1<-   0   0     FB6_11  52    I/O     I/O
DH0                   3       0   \/1   1     FB6_12  53    I/O     I
INTE_C                5       1<- \/1   0     FB6_13        (b)     (b)
REO                   6       1<-   0   0     FB6_14  54    I/O     O
INTE_B                5       0     0   0     FB6_15  55    I/O     I
INTE_A                5       0     0   0     FB6_16        (b)     (b)
SA_LOW<3>             5       0     0   0     FB6_17  56    I/O     O
GATE_ITRP             5       0     0   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0                  13: ISA_WR_DATA<1>.LFBK  25: CSEL 
  2: DA1                  14: ISA_WR_DATA<2>.LFBK  26: DMARQ 
  3: DA2                  15: ISA_WR_DATA<7>.LFBK  27: CS0n 
  4: DH0.LFBK             16: ITRP_STA<0>.LFBK     28: XLXI_620/XLXN_43 
  5: DH1.LFBK             17: RESET_CTL            29: RESETn 
  6: DH2.LFBK             18: WR_DATA_ENABLE       30: DMACKn 
  7: DH3.LFBK             19: DD<0>.PIN            31: CS1n 
  8: GATE_ITRP.LFBK       20: DD<1>.PIN            32: INT_A 
  9: INTE_A.LFBK          21: DD<2>.PIN            33: INT_B 
 10: INTE_B.LFBK          22: DD<3>.PIN            34: XLXN_48<3>.LFBK 
 11: INTE_C.LFBK          23: DD<7>.PIN            35: XLXN_49<2>.LFBK 
 12: ISA_WR_DATA<0>.LFBK  24: DIORn               

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXN_803<0>          ...............X........................ 1       1
SD<0>                XXXXXXX....X.....XX.....XXXXXXX......... 17      17
SA_HIGH<2>           XXXXXXX.............X...XXXXXXX...X..... 16      16
ITRP_STA<1>          .........X......X...........X...X....... 4       4
ITRP_STA<0>          ........X.......X...........X..X........ 4       4
SD<1>                XXXXXXX.....X....X.X....XXXXXXX......... 17      17
DH3                  XXX...X..............X...XX.XXX......... 10      10
SD<2>                XXXXXXX......X...X..X...XXXXXXX......... 17      17
DH2                  XXX..X..............X....XX.XXX......... 10      10
DH1                  XXX.X..............X.....XX.XXX......... 10      10
SD<7>                XXXXXXX.......X..X....X.XXXXXXX......... 17      17
DH0                  XXXX..............X......XX.XXX......... 10      10
INTE_C               XXXXXXX...X.........X...XXXXXXX......... 16      16
REO                  XXXXXXX................XXXXX.XX......... 14      14
INTE_B               XXXXXXX..X.........X....XXXXXXX......... 16      16
INTE_A               XXXXXXX.X.........X.....XXXXXXX......... 16      16
SA_LOW<3>            XXXXXXX..............X..XXXXXXX..X...... 16      16
GATE_ITRP            XXXXXXXX..............X.XXXXXXX......... 16      16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$$OpTx$FX_DC$20_INV$52 <= (NOT DA0 AND DA1 AND DA2);


$OpTx$FX_DC$18 <= NOT (CSEL
	 XOR 
$OpTx$FX_DC$18 <= NOT (XLXI_620/XLXN_43.LFBK);

FTCPE_AEN: FTCPE port map (AEN,AEN_T,DIOWn,'0',NOT RESETn);
AEN_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND XLXN_413.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXI_620/XLXN_43.LFBK AND XLXN_413.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND NOT XLXN_413.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXI_620/XLXN_43.LFBK AND NOT XLXN_413.LFBK));


DD_I(0) <= ((EXP4_.EXP)
	OR (WR_DATA_ENABLE.EXP)
	OR (NOT DA0 AND XLXN_802(0))
	OR (DA1 AND XLXN_802(0))
	OR (NOT DA2 AND XLXN_802(0))
	OR (NOT DMACKn AND XLXN_802(0))
	OR (NOT CS1n AND XLXN_802(0)));


DD_I(1) <= ((EXP0_.EXP)
	OR (EXP1_.EXP)
	OR (NOT DA0 AND XLXN_802(1))
	OR (DA1 AND XLXN_802(1))
	OR (NOT DA2 AND XLXN_802(1))
	OR (NOT DMACKn AND XLXN_802(1))
	OR (NOT CS1n AND XLXN_802(1)));


DD_I(2) <= ((EXP5_.EXP)
	OR (XLXN_769.EXP)
	OR (NOT DA0 AND XLXN_802(2))
	OR (DA1 AND XLXN_802(2))
	OR (NOT DA2 AND XLXN_802(2))
	OR (NOT DMACKn AND XLXN_802(2))
	OR (NOT CS1n AND XLXN_802(2)));


DD_I(3) <= ((XLXN_802(0).EXP)
	OR (EXP6_.EXP)
	OR (NOT DA0 AND XLXN_802(3))
	OR (DA1 AND XLXN_802(3))
	OR (NOT DA2 AND XLXN_802(3))
	OR (NOT DMACKn AND XLXN_802(3))
	OR (NOT CS1n AND XLXN_802(3)));


DD_I(4) <= ((EXP3_.EXP)
	OR (XLXN_803(7).EXP)
	OR (NOT DA0 AND XLXN_802(4).LFBK)
	OR (DA1 AND XLXN_802(4).LFBK)
	OR (NOT DA2 AND XLXN_802(4).LFBK)
	OR (NOT DMACKn AND XLXN_802(4).LFBK)
	OR (NOT CS1n AND XLXN_802(4).LFBK));


DD_I(5) <= ((EXP7_.EXP)
	OR (ISA_CLEAR.EXP)
	OR (NOT DA0 AND XLXN_802(5))
	OR (DA1 AND XLXN_802(5))
	OR (NOT DA2 AND XLXN_802(5))
	OR (NOT DMACKn AND XLXN_802(5))
	OR (NOT CS1n AND XLXN_802(5)));


DD_I(6) <= ((EXP8_.EXP)
	OR (EXP9_.EXP)
	OR (NOT DA0 AND XLXN_802(6))
	OR (DA1 AND XLXN_802(6))
	OR (NOT DA2 AND XLXN_802(6))
	OR (NOT DMACKn AND XLXN_802(6))
	OR (NOT CS1n AND XLXN_802(6)));


DD_I(7) <= ((EXP10_.EXP)
	OR (WR_REQUEST.EXP)
	OR (NOT DA0 AND XLXN_802(7))
	OR (DA1 AND XLXN_802(7))
	OR (NOT DA2 AND XLXN_802(7))
	OR (NOT DMACKn AND XLXN_802(7))
	OR (NOT CS1n AND XLXN_802(7)));

FTCPE_DH0: FTCPE port map (DH0,DH0_T,DIOWn,NOT RESETn,'0');
DH0_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(0).PIN AND NOT DH0.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(0).PIN AND DH0.LFBK));

FTCPE_DH1: FTCPE port map (DH1,DH1_T,DIOWn,NOT RESETn,'0');
DH1_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(1).PIN AND NOT DH1.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(1).PIN AND DH1.LFBK));

FTCPE_DH2: FTCPE port map (DH2,DH2_T,DIOWn,NOT RESETn,'0');
DH2_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(2).PIN AND NOT DH2.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(2).PIN AND DH2.LFBK));

FTCPE_DH3: FTCPE port map (DH3,DH3_T,DIOWn,NOT RESETn,'0');
DH3_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(3).PIN AND NOT DH3.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(3).PIN AND DH3.LFBK));























FTCPE_GATE_IORDY: FTCPE port map (GATE_IORDY,GATE_IORDY_T,DIOWn,NOT RESETn,'0');
GATE_IORDY_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND NOT GATE_IORDY.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXI_620/XLXN_43.LFBK AND NOT GATE_IORDY.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND GATE_IORDY.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXI_620/XLXN_43.LFBK AND GATE_IORDY.LFBK));

FTCPE_GATE_ITRP: FTCPE port map (GATE_ITRP,GATE_ITRP_T,DIOWn,NOT RESETn,'0');
GATE_ITRP_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(7).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT GATE_ITRP.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(7).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND GATE_ITRP.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(7).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT GATE_ITRP.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(7).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND GATE_ITRP.LFBK));

FTCPE_INTE_A: FTCPE port map (INTE_A,INTE_A_T,DIOWn,NOT RESETn,'0');
INTE_A_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(0).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_A.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(0).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_A.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(0).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_A.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(0).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_A.LFBK));

FTCPE_INTE_B: FTCPE port map (INTE_B,INTE_B_T,DIOWn,NOT RESETn,'0');
INTE_B_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(1).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_B.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(1).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_B.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(1).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_B.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(1).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_B.LFBK));

FTCPE_INTE_C: FTCPE port map (INTE_C,INTE_C_T,DIOWn,NOT RESETn,'0');
INTE_C_T <= ((DH0.EXP)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_C.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_C.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_C.LFBK));

FTCPE_INTE_D: FTCPE port map (INTE_D,INTE_D_T,DIOWn,NOT RESETn,'0');
INTE_D_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(3).PIN AND CSEL AND FC_0_.OUT AND 
	NOT INTE_D.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(3).PIN AND CSEL AND FC_0_.OUT AND 
	INTE_D.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(3).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT INTE_D.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(3).PIN AND NOT CSEL AND FC_0_.OUT AND 
	INTE_D.LFBK));


INTRQ_I <= NOT (FC_3_.OUT);
INTRQ <= INTRQ_I when INTRQ_OE = '1' else 'Z';
INTRQ_OE <= GATE_ITRP;


IORDY_I <= ((DIOWn AND DIORn)
	OR (NOT RD_PENDING AND ISA_WRITEn AND FC_1_.OUT));
IORDY <= IORDY_I when IORDY_OE = '1' else 'Z';
IORDY_OE <= (DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND FC_2_.OUT AND 
	GATE_IORDY.LFBK);


IORn <= NOT ((NOT ISA_READn AND ISA_PULSE.LFBK));


IOWn <= NOT ((ISA_PULSE AND NOT ISA_WRITEn));

FDCPE_ISA_PULSE: FDCPE port map (ISA_PULSE,ISA_PULSE_D,CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
ISA_PULSE_D <= ((NOT QSR(5) AND ISA_PULSE.LFBK)
	OR (NOT FC_4_.OUT AND IDLE.LFBK));

FDCPE_ISA_READn: FDCPE port map (ISA_READn,ISA_READn_D,CLK,'0',NOT XLXN_428/XLXN_428_SETF__$INT);
ISA_READn_D <= ((QSR(7) AND NOT WR_REQUEST AND RD_REQUEST)
	OR (NOT QSR(7) AND NOT SEQn AND NOT XLXN_428.LFBK)
	OR (NOT WR_REQUEST AND RD_REQUEST AND SEQn));


ISA_RESET <= NOT ((RESETn AND NOT RESET_CTL));

FDCPE_ISA_WRITEn: FDCPE port map (ISA_WRITEn,ISA_WRITEn_D,CLK,'0',NOT XLXN_428/XLXN_428_SETF__$INT);
ISA_WRITEn_D <= ((QSR(7) AND WR_REQUEST)
	OR (WR_REQUEST AND SEQn)
	OR (NOT QSR(7) AND NOT SEQn AND NOT XLXN_425.LFBK));

FDCPE_ITRP_STA0: FDCPE port map (ITRP_STA(0),'1',INT_A,ITRP_STA_CLR(0),'0');
ITRP_STA_CLR(0) <= (RESETn AND NOT RESET_CTL AND NOT INTE_A.LFBK);

FDCPE_ITRP_STA1: FDCPE port map (ITRP_STA(1),'1',INT_B,ITRP_STA_CLR(1),'0');
ITRP_STA_CLR(1) <= (RESETn AND NOT RESET_CTL AND NOT INTE_B.LFBK);

FDCPE_ITRP_STA2: FDCPE port map (ITRP_STA(2),'1',INT_C,ITRP_STA_CLR(2),'0');
ITRP_STA_CLR(2) <= (RESETn AND NOT INTE_C AND NOT RESET_CTL);

FDCPE_ITRP_STA3: FDCPE port map (ITRP_STA(3),'1',INT_D,ITRP_STA_CLR(3),'0');
ITRP_STA_CLR(3) <= (RESETn AND NOT RESET_CTL AND NOT INTE_D.LFBK);


ITRPn <= FC_3_.OUT;

FDCPE_QSR1: FDCPE port map (QSR(1),QSR_D(1),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
QSR_D(1) <= ((NOT SEQn AND NOT ISA_WRITEn AND NOT QSR(7).LFBK)
	OR (NOT SEQn AND NOT ISA_READn AND NOT QSR(7).LFBK)
	OR (ISA_WRITEn AND ISA_READn AND NOT QSR(7).LFBK AND 
	QSR(1).LFBK));

FDCPE_QSR2: FDCPE port map (QSR(2),QSR_D(2),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
QSR_D(2) <= ((NOT ISA_WRITEn AND NOT QSR(7).LFBK AND QSR(1).LFBK)
	OR (NOT ISA_READn AND NOT QSR(7).LFBK AND QSR(1).LFBK)
	OR (ISA_WRITEn AND ISA_READn AND NOT QSR(7).LFBK AND 
	QSR(2).LFBK));

FDCPE_QSR5: FDCPE port map (QSR(5),QSR_D(5),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
QSR_D(5) <= ((NOT ISA_WRITEn AND NOT QSR(7).LFBK AND XLXI_385/Q(4).LFBK)
	OR (NOT ISA_READn AND NOT QSR(7).LFBK AND XLXI_385/Q(4).LFBK)
	OR (ISA_WRITEn AND ISA_READn AND NOT QSR(7).LFBK AND 
	QSR(5).LFBK));

FDCPE_QSR6: FDCPE port map (QSR(6),QSR_D(6),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
QSR_D(6) <= ((NOT ISA_WRITEn AND NOT QSR(7).LFBK AND QSR(5).LFBK)
	OR (NOT ISA_READn AND NOT QSR(7).LFBK AND QSR(5).LFBK)
	OR (ISA_WRITEn AND ISA_READn AND NOT QSR(7).LFBK AND 
	QSR(6).LFBK));

FDCPE_QSR7: FDCPE port map (QSR(7),QSR_D(7),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
QSR_D(7) <= ((NOT ISA_WRITEn AND NOT QSR(7).LFBK AND QSR(6).LFBK)
	OR (NOT ISA_READn AND NOT QSR(7).LFBK AND QSR(6).LFBK));

FDCPE_RD_PENDING: FDCPE port map (RD_PENDING,RD_PENDING_D,NOT DIORn,RD_PENDING/RD_PENDING_RSTF.LFBK,'0');
RD_PENDING_D <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND CSEL AND FC_0_.OUT)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT CSEL AND FC_0_.OUT));


RD_PENDING/RD_PENDING_RSTF <= ((NOT RESETn)
	OR (RESET_CTL.LFBK)
	OR (NOT ISA_READn AND QSR(1).LFBK AND NOT QSR(2).LFBK));

FDCPE_RD_REQUEST: FDCPE port map (RD_REQUEST,RD_PENDING,CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');


REO <= ((INTE_C.EXP)
	OR (DA0 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DIORn AND 
	XLXI_620/XLXN_43 AND CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (DA0 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DIORn AND 
	NOT XLXI_620/XLXN_43 AND NOT CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DA1 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DIORn AND 
	XLXI_620/XLXN_43 AND CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DA1 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DIORn AND 
	NOT XLXI_620/XLXN_43 AND NOT CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND NOT DIORn AND 
	XLXI_620/XLXN_43 AND CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK));

FTCPE_RESET_CTL: FTCPE port map (RESET_CTL,RESET_CTL_T,DIOWn,NOT RESETn,'0');
RESET_CTL_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	NOT RESET_CTL.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	RESET_CTL.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT RESET_CTL.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	RESET_CTL.LFBK));

FTCPE_SA_HIGH0: FTCPE port map (SA_HIGH(0),SA_HIGH_T(0),DIOWn,NOT RESETn,'0');
SA_HIGH_T(0) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(0).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(0).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(0).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(0).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(0).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(0).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(0).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(0).LFBK));

FTCPE_SA_HIGH1: FTCPE port map (SA_HIGH(1),SA_HIGH_T(1),DIOWn,NOT RESETn,'0');
SA_HIGH_T(1) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(1).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(1).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(1).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(1).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(1).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(1).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(1).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(1).LFBK));

FTCPE_SA_HIGH2: FTCPE port map (SA_HIGH(2),SA_HIGH_T(2),DIOWn,NOT RESETn,'0');
SA_HIGH_T(2) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_49(2).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_49(2).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_49(2).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_49(2).LFBK));

FTCPE_SA_HIGH3: FTCPE port map (SA_HIGH(3),SA_HIGH_T(3),DIOWn,NOT RESETn,'0');
SA_HIGH_T(3) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(3).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(3).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(3).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(3).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(3).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(3).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(3).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(3).LFBK));

FTCPE_SA_HIGH4: FTCPE port map (SA_HIGH(4),SA_HIGH_T(4),DIOWn,NOT RESETn,'0');
SA_HIGH_T(4) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(4).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(4).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(4).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(4).LFBK));

FTCPE_SA_HIGH5: FTCPE port map (SA_HIGH(5),SA_HIGH_T(5),DIOWn,NOT RESETn,'0');
SA_HIGH_T(5) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(5).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(5).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(5).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(5).LFBK));

FTCPE_SA_HIGH6: FTCPE port map (SA_HIGH(6),SA_HIGH_T(6),DIOWn,NOT RESETn,'0');
SA_HIGH_T(6) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(6).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(6).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(6).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(6).LFBK));

FTCPE_SA_HIGH7: FTCPE port map (SA_HIGH(7),SA_HIGH_T(7),DIOWn,NOT RESETn,'0');
SA_HIGH_T(7) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(7).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(7).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(7).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_49(7).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(7).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_49(7).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(7).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_49(7).LFBK));

FTCPE_SA_LOW0: FTCPE port map (SA_LOW(0),SA_LOW_T(0),DIOWn,NOT RESETn,'0');
SA_LOW_T(0) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(0).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(0).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(0).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(0).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(0).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(0).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(0).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(0).LFBK));

FTCPE_SA_LOW1: FTCPE port map (SA_LOW(1),SA_LOW_T(1),DIOWn,NOT RESETn,'0');
SA_LOW_T(1) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(1).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(1).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(1).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(1).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(1).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(1).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(1).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(1).LFBK));

FTCPE_SA_LOW2: FTCPE port map (SA_LOW(2),SA_LOW_T(2),DIOWn,NOT RESETn,'0');
SA_LOW_T(2) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(2).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(2).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(2).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(2).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(2).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(2).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(2).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(2).LFBK));

FTCPE_SA_LOW3: FTCPE port map (SA_LOW(3),SA_LOW_T(3),DIOWn,NOT RESETn,'0');
SA_LOW_T(3) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(3).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_48(3).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(3).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_48(3).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(3).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_48(3).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(3).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_48(3).LFBK));

FTCPE_SA_LOW4: FTCPE port map (SA_LOW(4),SA_LOW_T(4),DIOWn,NOT RESETn,'0');
SA_LOW_T(4) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(4).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(4).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(4).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(4).LFBK));

FTCPE_SA_LOW5: FTCPE port map (SA_LOW(5),SA_LOW_T(5),DIOWn,NOT RESETn,'0');
SA_LOW_T(5) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(5).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(5).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(5).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(5).LFBK));

FTCPE_SA_LOW6: FTCPE port map (SA_LOW(6),SA_LOW_T(6),DIOWn,NOT RESETn,'0');
SA_LOW_T(6) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(6).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(6).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(6).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(6).LFBK));

FTCPE_SA_LOW7: FTCPE port map (SA_LOW(7),SA_LOW_T(7),DIOWn,NOT RESETn,'0');
SA_LOW_T(7) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(7).PIN AND CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(7).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(7).PIN AND CSEL AND FC_0_.OUT AND 
	XLXN_48(7).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(7).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXN_48(7).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(7).PIN AND NOT CSEL AND FC_0_.OUT AND 
	XLXN_48(7).LFBK));

FTCPE_SD0: FTCPE port map (SD_I(0),SD_T(0),DIOWn,NOT RESETn,'0');
SD_T(0) <= ((XLXN_803(0).EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(0).PIN AND CSEL AND 
	NOT ISA_WR_DATA(0).LFBK AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(0).PIN AND CSEL AND 
	ISA_WR_DATA(0).LFBK AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(0).PIN AND NOT CSEL AND 
	NOT ISA_WR_DATA(0).LFBK AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK));
SD(0) <= SD_I(0) when SD_OE(0) = '1' else 'Z';
SD_OE(0) <= WR_DATA_ENABLE;

FTCPE_SD1: FTCPE port map (SD_I(1),SD_T(1),DIOWn,NOT RESETn,'0');
SD_T(1) <= ((ITRP_STA(0).EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(1).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT ISA_WR_DATA(1).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(1).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND ISA_WR_DATA(1).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(1).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT ISA_WR_DATA(1).LFBK));
SD(1) <= SD_I(1) when SD_OE(1) = '1' else 'Z';
SD_OE(1) <= WR_DATA_ENABLE;

FTCPE_SD2: FTCPE port map (SD_I(2),SD_T(2),DIOWn,NOT RESETn,'0');
SD_T(2) <= ((DH3.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT ISA_WR_DATA(2).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND ISA_WR_DATA(2).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT ISA_WR_DATA(2).LFBK));
SD(2) <= SD_I(2) when SD_OE(2) = '1' else 'Z';
SD_OE(2) <= WR_DATA_ENABLE;

FTCPE_SD3: FTCPE port map (SD_I(3),SD_T(3),DIOWn,NOT RESETn,'0');
SD_T(3) <= ((EXP2_.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(3).PIN AND CSEL AND FC_0_.OUT AND 
	NOT ISA_WR_DATA(3).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(3).PIN AND CSEL AND FC_0_.OUT AND 
	ISA_WR_DATA(3).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT DD(3).PIN AND NOT CSEL AND FC_0_.OUT AND 
	ISA_WR_DATA(3).LFBK));
SD(3) <= SD_I(3) when SD_OE(3) = '1' else 'Z';
SD_OE(3) <= WR_DATA_ENABLE.LFBK;

FTCPE_SD4: FTCPE port map (SD_I(4),SD_T(4),DIOWn,NOT RESETn,'0');
SD_T(4) <= ((XLXN_803(6).EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	NOT ISA_WR_DATA(4).LFBK AND XLXI_620/XLXN_43.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(4).PIN AND CSEL AND FC_0_.OUT AND 
	ISA_WR_DATA(4).LFBK AND XLXI_620/XLXN_43.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(4).PIN AND NOT CSEL AND FC_0_.OUT AND 
	ISA_WR_DATA(4).LFBK AND NOT XLXI_620/XLXN_43.LFBK));
SD(4) <= SD_I(4) when SD_OE(4) = '1' else 'Z';
SD_OE(4) <= WR_DATA_ENABLE;

FTCPE_SD5: FTCPE port map (SD_I(5),SD_T(5),DIOWn,NOT RESETn,'0');
SD_T(5) <= ((XLXN_803(5).EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND NOT ISA_WR_DATA(5).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(5).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND ISA_WR_DATA(5).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(5).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXI_620/XLXN_43.LFBK AND ISA_WR_DATA(5).LFBK));
SD(5) <= SD_I(5) when SD_OE(5) = '1' else 'Z';
SD_OE(5) <= WR_DATA_ENABLE;

FTCPE_SD6: FTCPE port map (SD_I(6),SD_T(6),DIOWn,NOT RESETn,'0');
SD_T(6) <= (($OpTx$$OpTx$FX_DC$20_INV$52.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND NOT ISA_WR_DATA(6).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(6).PIN AND CSEL AND FC_0_.OUT AND 
	XLXI_620/XLXN_43.LFBK AND ISA_WR_DATA(6).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(6).PIN AND NOT CSEL AND FC_0_.OUT AND 
	NOT XLXI_620/XLXN_43.LFBK AND ISA_WR_DATA(6).LFBK));
SD(6) <= SD_I(6) when SD_OE(6) = '1' else 'Z';
SD_OE(6) <= WR_DATA_ENABLE;

FTCPE_SD7: FTCPE port map (SD_I(7),SD_T(7),DIOWn,NOT RESETn,'0');
SD_T(7) <= ((DH1.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND DD(7).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT ISA_WR_DATA(7).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND NOT DD(7).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND ISA_WR_DATA(7).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND DD(7).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT ISA_WR_DATA(7).LFBK));
SD(7) <= SD_I(7) when SD_OE(7) = '1' else 'Z';
SD_OE(7) <= WR_DATA_ENABLE;


SELECTEDn <= XLXI_620/XLXN_43.LFBK
	 XOR 
SELECTEDn <= CSEL;

FDCPE_SEQn: FDCPE port map (SEQn,SEQn_D,CLK,'0',NOT XLXN_428/XLXN_428_SETF__$INT);
SEQn_D <= ((QSR(7))
	OR (ISA_WRITEn AND ISA_READn AND IDLE.LFBK));

FDCPE_WR_DATA_ENABLE: FDCPE port map (WR_DATA_ENABLE,WR_DATA_ENABLE_D,CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
WR_DATA_ENABLE_D <= ((WR_REQUEST AND SEQn)
	OR (NOT QSR(6) AND WR_DATA_ENABLE.LFBK));

FDCPE_WR_PENDING: FDCPE port map (WR_PENDING,WR_PENDING_D,DIOWn,WR_PENDING/WR_PENDING_RSTF,'0');
WR_PENDING_D <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_620/XLXN_43 AND CSEL AND FC_0_.OUT)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_620/XLXN_43 AND NOT CSEL AND FC_0_.OUT));


WR_PENDING/WR_PENDING_RSTF <= ((NOT RESETn)
	OR (RESET_CTL.LFBK)
	OR (NOT ISA_WRITEn AND QSR(1).LFBK AND NOT QSR(2).LFBK));

FDCPE_WR_REQUEST: FDCPE port map (WR_REQUEST,WR_PENDING,CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');

FDCPE_XLXI_385/Q3: FDCPE port map (XLXI_385/Q(3),XLXI_385/Q_D(3),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
XLXI_385/Q_D(3) <= ((NOT ISA_WRITEn AND NOT QSR(7).LFBK AND QSR(2).LFBK)
	OR (NOT ISA_READn AND NOT QSR(7).LFBK AND QSR(2).LFBK)
	OR (ISA_WRITEn AND ISA_READn AND NOT QSR(7).LFBK AND 
	XLXI_385/Q(3).LFBK));

FDCPE_XLXI_385/Q4: FDCPE port map (XLXI_385/Q(4),XLXI_385/Q_D(4),CLK,NOT XLXN_428/XLXN_428_SETF__$INT,'0');
XLXI_385/Q_D(4) <= ((NOT ISA_WRITEn AND NOT QSR(7).LFBK AND XLXI_385/Q(3).LFBK)
	OR (NOT ISA_READn AND NOT QSR(7).LFBK AND XLXI_385/Q(3).LFBK)
	OR (ISA_WRITEn AND ISA_READn AND NOT QSR(7).LFBK AND 
	XLXI_385/Q(4).LFBK));

FTCPE_XLXI_620/XLXN_43: FTCPE port map (XLXI_620/XLXN_43,XLXI_620/XLXN_43_T,DIOWn,NOT RESETn,'0');
XLXI_620/XLXN_43_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(4).PIN AND NOT XLXI_620/XLXN_43.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(4).PIN AND XLXI_620/XLXN_43.LFBK));


XLXN_428/XLXN_428_SETF__$INT <= (RESETn AND NOT RESET_CTL);

FDCPE_XLXN_8020: FDCPE port map (XLXN_802(0),XLXN_802_D(0),CLK,'0','0');
XLXN_802_D(0) <= ((QSR(5) AND XLXN_802(0).LFBK)
	OR (NOT QSR(5) AND SD(0).PIN));

FDCPE_XLXN_8021: FDCPE port map (XLXN_802(1),XLXN_802_D(1),CLK,'0','0');
XLXN_802_D(1) <= ((QSR(5) AND XLXN_802(1).LFBK)
	OR (NOT QSR(5) AND SD(1).PIN));

FDCPE_XLXN_8022: FDCPE port map (XLXN_802(2),XLXN_802_D(2),CLK,'0','0');
XLXN_802_D(2) <= ((QSR(5) AND XLXN_802(2).LFBK)
	OR (NOT QSR(5) AND SD(2).PIN));

FDCPE_XLXN_8023: FDCPE port map (XLXN_802(3),XLXN_802_D(3),CLK,'0','0');
XLXN_802_D(3) <= ((QSR(5) AND XLXN_802(3).LFBK)
	OR (NOT QSR(5) AND SD(3).PIN));

FDCPE_XLXN_8024: FDCPE port map (XLXN_802(4),XLXN_802_D(4),CLK,'0','0');
XLXN_802_D(4) <= ((QSR(5) AND XLXN_802(4).LFBK)
	OR (NOT QSR(5) AND SD(4).PIN));

FDCPE_XLXN_8025: FDCPE port map (XLXN_802(5),XLXN_802_D(5),CLK,'0','0');
XLXN_802_D(5) <= ((QSR(5) AND XLXN_802(5).LFBK)
	OR (NOT QSR(5) AND SD(5).PIN));

FDCPE_XLXN_8026: FDCPE port map (XLXN_802(6),XLXN_802_D(6),CLK,'0','0');
XLXN_802_D(6) <= ((QSR(5) AND XLXN_802(6).LFBK)
	OR (NOT QSR(5) AND SD(6).PIN));

FDCPE_XLXN_8027: FDCPE port map (XLXN_802(7),XLXN_802_D(7),CLK,'0','0');
XLXN_802_D(7) <= ((QSR(5) AND XLXN_802(7).LFBK)
	OR (NOT QSR(5) AND SD(7).PIN));

FDCPE_XLXN_8030: FDCPE port map (XLXN_803(0),ITRP_STA(0).LFBK,NOT DIORn,'0','0');

FDCPE_XLXN_8031: FDCPE port map (XLXN_803(1),ITRP_STA(1),NOT DIORn,'0','0');

FDCPE_XLXN_8032: FDCPE port map (XLXN_803(2),ITRP_STA(2).LFBK,NOT DIORn,'0','0');

FDCPE_XLXN_8033: FDCPE port map (XLXN_803(3),ITRP_STA(3).LFBK,NOT DIORn,'0','0');

FDCPE_XLXN_8034: FDCPE port map (XLXN_803(4),'0',NOT DIORn,'0','0');

FDCPE_XLXN_8035: FDCPE port map (XLXN_803(5),'0',NOT DIORn,'0','0');

FDCPE_XLXN_8036: FDCPE port map (XLXN_803(6),'0',NOT DIORn,'0','0');

FDCPE_XLXN_8037: FDCPE port map (XLXN_803(7),'0',NOT DIORn,'0','0');

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


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  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
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 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 SD<4>                            43 CLK                           
  2 IOWn                             44 DD<0>                         
  3 SD<5>                            45 SD<0>                         
  4 CSEL                             46 SA_HIGH<2>                    
  5 SD<6>                            47 CS1n                          
  6 INT_D                            48 SD<1>                         
  7 AEN                              49 GND                           
  8 GND                              50 SD<2>                         
  9 DIOWn                            51 PGND                          
 10 DIORn                            52 SD<7>                         
 11 IORDY                            53 DA1                           
 12 PGND                             54 REO                           
 13 SELECTEDn                        55 RESETn                        
 14 DD<2>                            56 SA_LOW<3>                     
 15 INTRQ                            57 SA_LOW<4>                     
 16 GND                              58 SA_HIGH<6>                    
 17 DD<3>                            59 TDO                           
 18 INT_A                            60 GND                           
 19 DD<5>                            61 PGND                          
 20 ISA_RESET                        62 SA_LOW<5>                     
 21 DD<6>                            63 SA_LOW<6>                     
 22 VCC                              64 VCC                           
 23 PGND                             65 DMACKn                        
 24 DD<7>                            66 SA_HIGH<3>                    
 25 PGND                             67 INT_C                         
 26 IORn                             68 SA_HIGH<4>                    
 27 GND                              69 CS0n                          
 28 TDI                              70 SA_HIGH<5>                    
 29 TMS                              71 SA_LOW<0>                     
 30 TCK                              72 SA_LOW<1>                     
 31 SEQn                             73 VCC                           
 32 ISA_READn                        74 PGND                          
 33 ITRPn                            75 SA_LOW<2>                     
 34 DD<1>                            76 REI                           
 35 PGND                             77 PGND                          
 36 SD<3>                            78 VCC                           
 37 DA2                              79 SA_LOW<7>                     
 38 VCC                              80 SA_HIGH<0>                    
 39 DD<4>                            81 DMARQ                         
 40 INT_B                            82 SA_HIGH<1>                    
 41 ISA_WRITEn                       83 DA0                           
 42 GND                              84 SA_HIGH<7>                    


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Ground on Unused IOs                        : ON
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25