Design Name | ata_to_isa_06c |
Device, Speed (SpeedFile Version) | XC95108, -10 (3.0) |
Date Created | Sun Oct 08 12:31:31 2006 |
Created By | Timing Report Generator: version I.27 |
Copyright | Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
---|
Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
---|---|
Min. Clock Period | 16.000 ns. |
Max. Clock Frequency (fSYSTEM) | 62.500 MHz. |
Limited by Cycle Time for DIOWn | |
Clock to Setup (tCYC) | 16.000 ns. |
Pad to Pad Delay (tPD) | 23.000 ns. |
Setup to Clock at the Pad (tSU) | 7.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 28.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
TS1002 | 0.0 | 0.0 | 0 | 0 |
TS1003 | 0.0 | 0.0 | 0 | 0 |
TS1004 | 0.0 | 0.0 | 0 | 0 |
TS1005 | 0.0 | 0.0 | 0 | 0 |
TS1006 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 16.0 | 285 | 285 |
AUTO_TS_P2P | 0.0 | 28.5 | 170 | 170 |
AUTO_TS_P2F | 0.0 | 9.5 | 380 | 380 |
AUTO_TS_F2P | 0.0 | 23.5 | 118 | 118 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
DH0.Q to SD<3>.D | 0.000 | 16.000 | -16.000 |
DH0.Q to SD<4>.D | 0.000 | 16.000 | -16.000 |
DH0.Q to SD<5>.D | 0.000 | 16.000 | -16.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CLK to DD<0> | 0.000 | 28.500 | -28.500 |
CLK to DD<1> | 0.000 | 28.500 | -28.500 |
CLK to DD<2> | 0.000 | 28.500 | -28.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CS0n to INTE_C.D | 0.000 | 9.500 | -9.500 |
CS0n to SD<0>.D | 0.000 | 9.500 | -9.500 |
CS0n to SD<1>.D | 0.000 | 9.500 | -9.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
XLXI_620/XLXN_43.Q to IORDY | 0.000 | 23.500 | -23.500 |
DH0.Q to DD<0> | 0.000 | 23.000 | -23.000 |
DH1.Q to DD<0> | 0.000 | 23.000 | -23.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
INT_D | 83.333 | Limited by Clock Pulse Width for INT_D |
INT_C | 83.333 | Limited by Clock Pulse Width for INT_C |
INT_B | 83.333 | Limited by Clock Pulse Width for INT_B |
INT_A | 83.333 | Limited by Clock Pulse Width for INT_A |
DIORn | 111.111 | Limited by Clock Pulse Width for DIORn |
CLK | 66.667 | Limited by Cycle Time for CLK |
DIOWn | 62.500 | Limited by Cycle Time for DIOWn |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
CS0n | 6.000 | 0.000 |
CS1n | 6.000 | 0.000 |
CSEL | 6.000 | 0.000 |
DA0 | 6.000 | 0.000 |
DA1 | 6.000 | 0.000 |
DA2 | 6.000 | 0.000 |
DMACKn | 6.000 | 0.000 |
DMARQ | 6.000 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
SD<0> | 2.000 | 1.500 |
SD<1> | 2.000 | 1.500 |
SD<2> | 2.000 | 1.500 |
SD<3> | 2.000 | 1.500 |
SD<4> | 2.000 | 1.500 |
SD<5> | 2.000 | 1.500 |
SD<6> | 2.000 | 1.500 |
SD<7> | 2.000 | 1.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
CS0n | 7.000 | 0.000 |
CS1n | 7.000 | 0.000 |
CSEL | 7.000 | 0.000 |
DA0 | 7.000 | 0.000 |
DA1 | 7.000 | 0.000 |
DA2 | 7.000 | 0.000 |
DD<0> | 7.000 | 0.000 |
DD<1> | 7.000 | 0.000 |
DD<2> | 7.000 | 0.000 |
DD<3> | 7.000 | 0.000 |
DD<4> | 7.000 | 0.000 |
DD<5> | 7.000 | 0.000 |
DD<6> | 7.000 | 0.000 |
DD<7> | 7.000 | 0.000 |
DMACKn | 7.000 | 0.000 |
DMARQ | 7.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
INTRQ | 27.500 |
ITRPn | 27.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
INTRQ | 27.500 |
ITRPn | 27.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
INTRQ | 27.500 |
ITRPn | 27.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
INTRQ | 27.500 |
ITRPn | 27.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
DD<0> | 25.500 |
DD<1> | 24.500 |
DD<2> | 24.500 |
DD<3> | 24.500 |
DD<4> | 24.500 |
DD<5> | 24.500 |
DD<6> | 24.500 |
DD<7> | 24.500 |
IORDY | 23.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
DD<0> | 28.500 |
DD<1> | 28.500 |
DD<2> | 28.500 |
DD<3> | 28.500 |
DD<5> | 28.500 |
DD<6> | 28.500 |
DD<7> | 28.500 |
IORDY | 27.500 |
IORn | 27.500 |
IOWn | 27.500 |
SD<0> | 23.000 |
SD<1> | 23.000 |
SD<2> | 23.000 |
SD<4> | 23.000 |
SD<5> | 23.000 |
SD<6> | 23.000 |
SD<7> | 23.000 |
DD<4> | 22.500 |
SD<3> | 17.000 |
ISA_READn | 14.500 |
ISA_WRITEn | 14.500 |
SEQn | 14.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
IORDY | 26.000 |
DD<0> | 25.500 |
DD<1> | 24.500 |
DD<2> | 24.500 |
DD<3> | 24.500 |
DD<4> | 24.500 |
DD<5> | 24.500 |
DD<6> | 24.500 |
DD<7> | 24.500 |
REO | 24.500 |
ISA_RESET | 23.500 |
INTRQ | 19.000 |
SELECTEDn | 17.500 |
AEN | 10.500 |
SA_HIGH<0> | 10.500 |
SA_HIGH<1> | 10.500 |
SA_HIGH<2> | 10.500 |
SA_HIGH<3> | 10.500 |
SA_HIGH<4> | 10.500 |
SA_HIGH<5> | 10.500 |
SA_HIGH<6> | 10.500 |
SA_HIGH<7> | 10.500 |
SA_LOW<0> | 10.500 |
SA_LOW<1> | 10.500 |
SA_LOW<2> | 10.500 |
SA_LOW<3> | 10.500 |
SA_LOW<4> | 10.500 |
SA_LOW<5> | 10.500 |
SA_LOW<6> | 10.500 |
SA_LOW<7> | 10.500 |
SD<0> | 10.500 |
SD<1> | 10.500 |
SD<2> | 10.500 |
SD<3> | 10.500 |
SD<4> | 10.500 |
SD<5> | 10.500 |
SD<6> | 10.500 |
SD<7> | 10.500 |
Source | Destination | Delay |
---|---|---|
ISA_READn.Q | QSR<1>.D | 15.000 |
ISA_READn.Q | QSR<2>.D | 15.000 |
ISA_READn.Q | QSR<5>.D | 15.000 |
ISA_READn.Q | QSR<6>.D | 15.000 |
ISA_READn.Q | QSR<7>.D | 15.000 |
ISA_READn.Q | SEQn.D | 15.000 |
ISA_READn.Q | XLXI_385/Q<3>.D | 15.000 |
ISA_READn.Q | XLXI_385/Q<4>.D | 15.000 |
ISA_WRITEn.Q | QSR<1>.D | 15.000 |
ISA_WRITEn.Q | QSR<2>.D | 15.000 |
ISA_WRITEn.Q | QSR<5>.D | 15.000 |
ISA_WRITEn.Q | QSR<6>.D | 15.000 |
ISA_WRITEn.Q | QSR<7>.D | 15.000 |
ISA_WRITEn.Q | SEQn.D | 15.000 |
ISA_WRITEn.Q | XLXI_385/Q<3>.D | 15.000 |
ISA_WRITEn.Q | XLXI_385/Q<4>.D | 15.000 |
QSR<5>.Q | ISA_PULSE.D | 15.000 |
QSR<5>.Q | XLXN_802<0>.D | 15.000 |
QSR<5>.Q | XLXN_802<1>.D | 15.000 |
QSR<5>.Q | XLXN_802<2>.D | 15.000 |
QSR<5>.Q | XLXN_802<3>.D | 15.000 |
QSR<5>.Q | XLXN_802<4>.D | 15.000 |
QSR<5>.Q | XLXN_802<5>.D | 15.000 |
QSR<5>.Q | XLXN_802<6>.D | 15.000 |
QSR<5>.Q | XLXN_802<7>.D | 15.000 |
QSR<6>.Q | WR_DATA_ENABLE.D | 15.000 |
QSR<7>.Q | ISA_READn.D | 15.000 |
QSR<7>.Q | ISA_WRITEn.D | 15.000 |
QSR<7>.Q | SEQn.D | 15.000 |
RD_REQUEST.Q | ISA_PULSE.D | 15.000 |
RD_REQUEST.Q | ISA_READn.D | 15.000 |
SEQn.Q | ISA_READn.D | 15.000 |
SEQn.Q | ISA_WRITEn.D | 15.000 |
SEQn.Q | QSR<1>.D | 15.000 |
SEQn.Q | WR_DATA_ENABLE.D | 15.000 |
WR_REQUEST.Q | ISA_PULSE.D | 15.000 |
WR_REQUEST.Q | ISA_READn.D | 15.000 |
WR_REQUEST.Q | ISA_WRITEn.D | 15.000 |
WR_REQUEST.Q | WR_DATA_ENABLE.D | 15.000 |
ISA_PULSE.Q | ISA_PULSE.D | 9.000 |
ISA_READn.Q | ISA_READn.D | 9.000 |
ISA_WRITEn.Q | ISA_WRITEn.D | 9.000 |
QSR<1>.Q | QSR<1>.D | 9.000 |
QSR<1>.Q | QSR<2>.D | 9.000 |
QSR<2>.Q | QSR<2>.D | 9.000 |
QSR<2>.Q | XLXI_385/Q<3>.D | 9.000 |
QSR<5>.Q | QSR<5>.D | 9.000 |
QSR<5>.Q | QSR<6>.D | 9.000 |
QSR<6>.Q | QSR<6>.D | 9.000 |
QSR<6>.Q | QSR<7>.D | 9.000 |
QSR<7>.Q | QSR<1>.D | 9.000 |
QSR<7>.Q | QSR<2>.D | 9.000 |
QSR<7>.Q | QSR<5>.D | 9.000 |
QSR<7>.Q | QSR<6>.D | 9.000 |
QSR<7>.Q | QSR<7>.D | 9.000 |
QSR<7>.Q | XLXI_385/Q<3>.D | 9.000 |
QSR<7>.Q | XLXI_385/Q<4>.D | 9.000 |
SEQn.Q | ISA_PULSE.D | 9.000 |
SEQn.Q | SEQn.D | 9.000 |
WR_DATA_ENABLE.Q | WR_DATA_ENABLE.D | 9.000 |
XLXI_385/Q<3>.Q | XLXI_385/Q<3>.D | 9.000 |
XLXI_385/Q<3>.Q | XLXI_385/Q<4>.D | 9.000 |
XLXI_385/Q<4>.Q | QSR<5>.D | 9.000 |
XLXI_385/Q<4>.Q | XLXI_385/Q<4>.D | 9.000 |
XLXN_802<0>.Q | XLXN_802<0>.D | 9.000 |
XLXN_802<1>.Q | XLXN_802<1>.D | 9.000 |
XLXN_802<2>.Q | XLXN_802<2>.D | 9.000 |
XLXN_802<3>.Q | XLXN_802<3>.D | 9.000 |
XLXN_802<4>.Q | XLXN_802<4>.D | 9.000 |
XLXN_802<5>.Q | XLXN_802<5>.D | 9.000 |
XLXN_802<6>.Q | XLXN_802<6>.D | 9.000 |
XLXN_802<7>.Q | XLXN_802<7>.D | 9.000 |
Source | Destination | Delay |
---|---|---|
DH0.Q | SD<3>.D | 16.000 |
DH0.Q | SD<4>.D | 16.000 |
DH0.Q | SD<5>.D | 16.000 |
DH0.Q | SD<6>.D | 16.000 |
DH1.Q | SD<3>.D | 16.000 |
DH1.Q | SD<4>.D | 16.000 |
DH1.Q | SD<5>.D | 16.000 |
DH1.Q | SD<6>.D | 16.000 |
DH2.Q | SD<3>.D | 16.000 |
DH2.Q | SD<4>.D | 16.000 |
DH2.Q | SD<5>.D | 16.000 |
DH2.Q | SD<6>.D | 16.000 |
DH3.Q | SD<3>.D | 16.000 |
DH3.Q | SD<4>.D | 16.000 |
DH3.Q | SD<5>.D | 16.000 |
DH3.Q | SD<6>.D | 16.000 |
XLXI_620/XLXN_43.Q | INTE_C.D | 16.000 |
XLXI_620/XLXN_43.Q | SD<0>.D | 16.000 |
XLXI_620/XLXN_43.Q | SD<1>.D | 16.000 |
XLXI_620/XLXN_43.Q | SD<2>.D | 16.000 |
XLXI_620/XLXN_43.Q | SD<3>.D | 16.000 |
XLXI_620/XLXN_43.Q | SD<7>.D | 16.000 |
DH0.Q | AEN.D | 15.000 |
DH0.Q | GATE_IORDY.D | 15.000 |
DH0.Q | INTE_D.D | 15.000 |
DH0.Q | RESET_CTL.D | 15.000 |
DH0.Q | SA_HIGH<0>.D | 15.000 |
DH0.Q | SA_HIGH<1>.D | 15.000 |
DH0.Q | SA_HIGH<3>.D | 15.000 |
DH0.Q | SA_HIGH<4>.D | 15.000 |
DH0.Q | SA_HIGH<5>.D | 15.000 |
DH0.Q | SA_HIGH<6>.D | 15.000 |
DH0.Q | SA_HIGH<7>.D | 15.000 |
DH0.Q | SA_LOW<0>.D | 15.000 |
DH0.Q | SA_LOW<1>.D | 15.000 |
DH0.Q | SA_LOW<2>.D | 15.000 |
DH0.Q | SA_LOW<4>.D | 15.000 |
DH0.Q | SA_LOW<5>.D | 15.000 |
DH0.Q | SA_LOW<6>.D | 15.000 |
DH0.Q | SA_LOW<7>.D | 15.000 |
DH0.Q | WR_PENDING.D | 15.000 |
DH1.Q | AEN.D | 15.000 |
DH1.Q | GATE_IORDY.D | 15.000 |
DH1.Q | INTE_D.D | 15.000 |
DH1.Q | RESET_CTL.D | 15.000 |
DH1.Q | SA_HIGH<0>.D | 15.000 |
DH1.Q | SA_HIGH<1>.D | 15.000 |
DH1.Q | SA_HIGH<3>.D | 15.000 |
DH1.Q | SA_HIGH<4>.D | 15.000 |
DH1.Q | SA_HIGH<5>.D | 15.000 |
DH1.Q | SA_HIGH<6>.D | 15.000 |
DH1.Q | SA_HIGH<7>.D | 15.000 |
DH1.Q | SA_LOW<0>.D | 15.000 |
DH1.Q | SA_LOW<1>.D | 15.000 |
DH1.Q | SA_LOW<2>.D | 15.000 |
DH1.Q | SA_LOW<4>.D | 15.000 |
DH1.Q | SA_LOW<5>.D | 15.000 |
DH1.Q | SA_LOW<6>.D | 15.000 |
DH1.Q | SA_LOW<7>.D | 15.000 |
DH1.Q | WR_PENDING.D | 15.000 |
DH2.Q | AEN.D | 15.000 |
DH2.Q | GATE_IORDY.D | 15.000 |
DH2.Q | INTE_D.D | 15.000 |
DH2.Q | RESET_CTL.D | 15.000 |
DH2.Q | SA_HIGH<0>.D | 15.000 |
DH2.Q | SA_HIGH<1>.D | 15.000 |
DH2.Q | SA_HIGH<3>.D | 15.000 |
DH2.Q | SA_HIGH<4>.D | 15.000 |
DH2.Q | SA_HIGH<5>.D | 15.000 |
DH2.Q | SA_HIGH<6>.D | 15.000 |
DH2.Q | SA_HIGH<7>.D | 15.000 |
DH2.Q | SA_LOW<0>.D | 15.000 |
DH2.Q | SA_LOW<1>.D | 15.000 |
DH2.Q | SA_LOW<2>.D | 15.000 |
DH2.Q | SA_LOW<4>.D | 15.000 |
DH2.Q | SA_LOW<5>.D | 15.000 |
DH2.Q | SA_LOW<6>.D | 15.000 |
DH2.Q | SA_LOW<7>.D | 15.000 |
DH2.Q | WR_PENDING.D | 15.000 |
DH3.Q | AEN.D | 15.000 |
DH3.Q | GATE_IORDY.D | 15.000 |
DH3.Q | INTE_D.D | 15.000 |
DH3.Q | RESET_CTL.D | 15.000 |
DH3.Q | SA_HIGH<0>.D | 15.000 |
DH3.Q | SA_HIGH<1>.D | 15.000 |
DH3.Q | SA_HIGH<3>.D | 15.000 |
DH3.Q | SA_HIGH<4>.D | 15.000 |
DH3.Q | SA_HIGH<5>.D | 15.000 |
DH3.Q | SA_HIGH<6>.D | 15.000 |
DH3.Q | SA_HIGH<7>.D | 15.000 |
DH3.Q | SA_LOW<0>.D | 15.000 |
DH3.Q | SA_LOW<1>.D | 15.000 |
DH3.Q | SA_LOW<2>.D | 15.000 |
DH3.Q | SA_LOW<4>.D | 15.000 |
DH3.Q | SA_LOW<5>.D | 15.000 |
DH3.Q | SA_LOW<6>.D | 15.000 |
DH3.Q | SA_LOW<7>.D | 15.000 |
DH3.Q | WR_PENDING.D | 15.000 |
XLXI_620/XLXN_43.Q | GATE_ITRP.D | 15.000 |
XLXI_620/XLXN_43.Q | INTE_A.D | 15.000 |
XLXI_620/XLXN_43.Q | INTE_B.D | 15.000 |
XLXI_620/XLXN_43.Q | INTE_D.D | 15.000 |
XLXI_620/XLXN_43.Q | RESET_CTL.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<0>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<1>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<2>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<3>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<4>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<5>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<6>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_HIGH<7>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<0>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<1>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<2>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<3>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<4>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<5>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<6>.D | 15.000 |
XLXI_620/XLXN_43.Q | SA_LOW<7>.D | 15.000 |
XLXI_620/XLXN_43.Q | WR_PENDING.D | 15.000 |
DH0.Q | INTE_C.D | 10.000 |
DH0.Q | SD<0>.D | 10.000 |
DH0.Q | SD<1>.D | 10.000 |
DH0.Q | SD<2>.D | 10.000 |
DH0.Q | SD<7>.D | 10.000 |
DH1.Q | INTE_C.D | 10.000 |
DH1.Q | SD<0>.D | 10.000 |
DH1.Q | SD<1>.D | 10.000 |
DH1.Q | SD<2>.D | 10.000 |
DH1.Q | SD<7>.D | 10.000 |
DH2.Q | INTE_C.D | 10.000 |
DH2.Q | SD<0>.D | 10.000 |
DH2.Q | SD<1>.D | 10.000 |
DH2.Q | SD<2>.D | 10.000 |
DH2.Q | SD<7>.D | 10.000 |
DH3.Q | INTE_C.D | 10.000 |
DH3.Q | SD<0>.D | 10.000 |
DH3.Q | SD<1>.D | 10.000 |
DH3.Q | SD<2>.D | 10.000 |
DH3.Q | SD<7>.D | 10.000 |
INTE_C.Q | INTE_C.D | 10.000 |
SD<0>.Q | SD<0>.D | 10.000 |
SD<1>.Q | SD<1>.D | 10.000 |
SD<2>.Q | SD<2>.D | 10.000 |
SD<3>.Q | SD<3>.D | 10.000 |
SD<4>.Q | SD<4>.D | 10.000 |
SD<5>.Q | SD<5>.D | 10.000 |
SD<6>.Q | SD<6>.D | 10.000 |
SD<7>.Q | SD<7>.D | 10.000 |
XLXI_620/XLXN_43.Q | SD<4>.D | 10.000 |
XLXI_620/XLXN_43.Q | SD<5>.D | 10.000 |
XLXI_620/XLXN_43.Q | SD<6>.D | 10.000 |
AEN.Q | AEN.D | 9.000 |
DH0.Q | DH0.D | 9.000 |
DH0.Q | GATE_ITRP.D | 9.000 |
DH0.Q | INTE_A.D | 9.000 |
DH0.Q | INTE_B.D | 9.000 |
DH0.Q | SA_HIGH<2>.D | 9.000 |
DH0.Q | SA_LOW<3>.D | 9.000 |
DH1.Q | DH1.D | 9.000 |
DH1.Q | GATE_ITRP.D | 9.000 |
DH1.Q | INTE_A.D | 9.000 |
DH1.Q | INTE_B.D | 9.000 |
DH1.Q | SA_HIGH<2>.D | 9.000 |
DH1.Q | SA_LOW<3>.D | 9.000 |
DH2.Q | DH2.D | 9.000 |
DH2.Q | GATE_ITRP.D | 9.000 |
DH2.Q | INTE_A.D | 9.000 |
DH2.Q | INTE_B.D | 9.000 |
DH2.Q | SA_HIGH<2>.D | 9.000 |
DH2.Q | SA_LOW<3>.D | 9.000 |
DH3.Q | DH3.D | 9.000 |
DH3.Q | GATE_ITRP.D | 9.000 |
DH3.Q | INTE_A.D | 9.000 |
DH3.Q | INTE_B.D | 9.000 |
DH3.Q | SA_HIGH<2>.D | 9.000 |
DH3.Q | SA_LOW<3>.D | 9.000 |
GATE_IORDY.Q | GATE_IORDY.D | 9.000 |
GATE_ITRP.Q | GATE_ITRP.D | 9.000 |
INTE_A.Q | INTE_A.D | 9.000 |
INTE_B.Q | INTE_B.D | 9.000 |
INTE_D.Q | INTE_D.D | 9.000 |
RESET_CTL.Q | RESET_CTL.D | 9.000 |
SA_HIGH<0>.Q | SA_HIGH<0>.D | 9.000 |
SA_HIGH<1>.Q | SA_HIGH<1>.D | 9.000 |
SA_HIGH<2>.Q | SA_HIGH<2>.D | 9.000 |
SA_HIGH<3>.Q | SA_HIGH<3>.D | 9.000 |
SA_HIGH<4>.Q | SA_HIGH<4>.D | 9.000 |
SA_HIGH<5>.Q | SA_HIGH<5>.D | 9.000 |
SA_HIGH<6>.Q | SA_HIGH<6>.D | 9.000 |
SA_HIGH<7>.Q | SA_HIGH<7>.D | 9.000 |
SA_LOW<0>.Q | SA_LOW<0>.D | 9.000 |
SA_LOW<1>.Q | SA_LOW<1>.D | 9.000 |
SA_LOW<2>.Q | SA_LOW<2>.D | 9.000 |
SA_LOW<3>.Q | SA_LOW<3>.D | 9.000 |
SA_LOW<4>.Q | SA_LOW<4>.D | 9.000 |
SA_LOW<5>.Q | SA_LOW<5>.D | 9.000 |
SA_LOW<6>.Q | SA_LOW<6>.D | 9.000 |
SA_LOW<7>.Q | SA_LOW<7>.D | 9.000 |
XLXI_620/XLXN_43.Q | AEN.D | 9.000 |
XLXI_620/XLXN_43.Q | GATE_IORDY.D | 9.000 |
XLXI_620/XLXN_43.Q | XLXI_620/XLXN_43.D | 9.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
CSEL | IORDY | 23.000 |
DA0 | IORDY | 23.000 |
DA1 | IORDY | 23.000 |
DA2 | IORDY | 23.000 |
CS0n | DD<0> | 16.500 |
CS1n | DD<0> | 16.500 |
CSEL | DD<0> | 16.500 |
DA0 | DD<0> | 16.500 |
DA1 | DD<0> | 16.500 |
DA2 | DD<0> | 16.500 |
DMACKn | DD<0> | 16.500 |
DMARQ | DD<0> | 16.500 |
CS0n | DD<1> | 15.500 |
CS0n | DD<2> | 15.500 |
CS0n | DD<3> | 15.500 |
CS0n | DD<4> | 15.500 |
CS0n | DD<5> | 15.500 |
CS0n | DD<6> | 15.500 |
CS0n | DD<7> | 15.500 |
CS0n | REO | 15.500 |
CS1n | DD<1> | 15.500 |
CS1n | DD<2> | 15.500 |
CS1n | DD<3> | 15.500 |
CS1n | DD<4> | 15.500 |
CS1n | DD<5> | 15.500 |
CS1n | DD<6> | 15.500 |
CS1n | DD<7> | 15.500 |
CS1n | REO | 15.500 |
CSEL | DD<1> | 15.500 |
CSEL | DD<2> | 15.500 |
CSEL | DD<3> | 15.500 |
CSEL | DD<4> | 15.500 |
CSEL | DD<5> | 15.500 |
CSEL | DD<6> | 15.500 |
CSEL | DD<7> | 15.500 |
CSEL | REO | 15.500 |
DA0 | DD<1> | 15.500 |
DA0 | DD<2> | 15.500 |
DA0 | DD<3> | 15.500 |
DA0 | DD<4> | 15.500 |
DA0 | DD<5> | 15.500 |
DA0 | DD<6> | 15.500 |
DA0 | DD<7> | 15.500 |
DA1 | DD<1> | 15.500 |
DA1 | DD<2> | 15.500 |
DA1 | DD<3> | 15.500 |
DA1 | DD<4> | 15.500 |
DA1 | DD<5> | 15.500 |
DA1 | DD<6> | 15.500 |
DA1 | DD<7> | 15.500 |
DA2 | DD<1> | 15.500 |
DA2 | DD<2> | 15.500 |
DA2 | DD<3> | 15.500 |
DA2 | DD<4> | 15.500 |
DA2 | DD<5> | 15.500 |
DA2 | DD<6> | 15.500 |
DA2 | DD<7> | 15.500 |
DA2 | REO | 15.500 |
DIORn | REO | 15.500 |
DMACKn | DD<1> | 15.500 |
DMACKn | DD<2> | 15.500 |
DMACKn | DD<3> | 15.500 |
DMACKn | DD<4> | 15.500 |
DMACKn | DD<5> | 15.500 |
DMACKn | DD<6> | 15.500 |
DMACKn | DD<7> | 15.500 |
DMACKn | REO | 15.500 |
DMARQ | DD<1> | 15.500 |
DMARQ | DD<2> | 15.500 |
DMARQ | DD<3> | 15.500 |
DMARQ | DD<4> | 15.500 |
DMARQ | DD<5> | 15.500 |
DMARQ | DD<6> | 15.500 |
DMARQ | DD<7> | 15.500 |
DMARQ | REO | 15.500 |
CSEL | SELECTEDn | 14.500 |
DA0 | REO | 14.500 |
DA1 | REO | 14.500 |
DIORn | IORDY | 14.500 |
DIOWn | IORDY | 14.500 |
RESETn | ISA_RESET | 14.500 |
CS0n | IORDY | 10.000 |
CS1n | IORDY | 10.000 |
DMACKn | IORDY | 10.000 |
DMARQ | IORDY | 10.000 |
REI | DD<0> | 6.000 |
REI | DD<1> | 6.000 |
REI | DD<2> | 6.000 |
REI | DD<3> | 6.000 |
REI | DD<4> | 6.000 |
REI | DD<5> | 6.000 |
REI | DD<6> | 6.000 |
REI | DD<7> | 6.000 |