cpldfit:  version I.27                              Xilinx Inc.
                                  Fitter Report
Design Name: ata_to_isa_06a                      Date: 10- 6-2006,  8:09PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
64 /108 ( 59%) 298 /540  ( 55%) 172/216 ( 80%)   52 /108 ( 48%) 59 /69  ( 85%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           6/18       23/36       23          26/90       6/12
FB2          10/18       31/36       31          41/90       7/12
FB3          14/18       31/36       31          70/90       9/12
FB4           8/18       27/36       27          37/90       7/11
FB5          10/18       29/36       29          55/90       7/11
FB6          16/18       31/36       31          69/90       7/11
             -----       -----                   -----       -----     
             64/108     172/216                 298/540     43/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'DIOWn' mapped onto global clock net GCK1.
The complement of 'DIOWn' mapped onto global clock net GCK3.
Signal 'REI' mapped onto global output enable net GTS1.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   14          14    |  I/O              :    56      63
Output        :   27          27    |  GCK/IO           :     2       3
Bidirectional :   16          16    |  GTS/IO           :     1       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    1           1    |
GSR           :    0           0    |
                 ----        ----
        Total     59          59

** Power Data **

There are 64 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 43 Outputs **

Signal                              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                Pts   Inps          No.  Type    Use     Mode Rate State
SD<4>                               6     18    FB1_2   1    I/O     I/O     STD  SLOW RESET
IOWn                                1     2     FB1_3   2    I/O     O       STD  SLOW 
SD<5>                               6     18    FB1_5   3    I/O     I/O     STD  SLOW RESET
SD<6>                               6     18    FB1_8   5    I/O     I/O     STD  SLOW RESET
AEN                                 5     16    FB1_11  7    I/O     O       STD  SLOW SET
SELECTEDn                           2     2     FB1_17  13   I/O     O       STD  SLOW 
SA_LOW<0>                           5     16    FB2_2   71   I/O     O       STD  SLOW RESET
SA_LOW<1>                           5     16    FB2_3   72   I/O     O       STD  SLOW RESET
SA_LOW<2>                           5     16    FB2_6   75   I/O     O       STD  SLOW RESET
SA_LOW<7>                           5     16    FB2_11  79   I/O     O       STD  SLOW RESET
SA_HIGH<0>                          5     16    FB2_12  80   I/O     O       STD  SLOW RESET
SA_HIGH<1>                          5     16    FB2_15  82   I/O     O       STD  SLOW RESET
SA_HIGH<7>                          5     16    FB2_17  84   I/O     O       STD  SLOW RESET
DD<2>                               16    16    FB3_2   14   I/O     I/O     STD  SLOW RESET
INTRQ                               2     5     FB3_3   15   I/O     O       STD  SLOW 
DD<3>                               16    16    FB3_5   17   I/O     I/O     STD  SLOW RESET
DD<5>                               4     15    FB3_8   19   I/O     I/O     STD  SLOW RESET
ISA_RESET                           1     2     FB3_9   20   I/O     O       STD  SLOW 
DD<6>                               4     15    FB3_11  21   I/O     I/O     STD  SLOW RESET
DD<7>                               4     15    FB3_14  24   I/O     I/O     STD  SLOW RESET
IORn                                4     16    FB3_16  26   I/O     O       STD  SLOW SET
RD_STATEn                           4     16    FB3_17  31   I/O     O       STD  SLOW SET
SA_LOW<4>                           5     16    FB4_2   57   I/O     O       STD  SLOW RESET
SA_HIGH<6>                          5     16    FB4_3   58   I/O     O       STD  SLOW RESET
SA_LOW<5>                           5     16    FB4_6   62   I/O     O       STD  SLOW RESET
SA_LOW<6>                           5     16    FB4_8   63   I/O     O       STD  SLOW RESET
SA_HIGH<3>                          5     16    FB4_11  66   I/O     O       STD  SLOW RESET
SA_HIGH<4>                          5     16    FB4_14  68   I/O     O       STD  SLOW RESET
SA_HIGH<5>                          5     16    FB4_17  70   I/O     O       STD  SLOW RESET
WR_STATE_2n                         2     2     FB5_2   32   I/O     O       STD  SLOW SET
ITRPn                               1     4     FB5_3   33   I/O     O       STD  SLOW 
DD<1>                               16    16    FB5_5   34   I/O     I/O     STD  SLOW RESET
SD<3>                               6     18    FB5_8   36   I/O     I/O     STD  SLOW RESET
DD<4>                               4     15    FB5_11  39   I/O     I/O     STD  SLOW RESET
WR_STATE_1n                         3     15    FB5_14  41   I/O     O       STD  SLOW SET
DD<0>                               16    16    FB5_17  44   I/O     I/O     STD  SLOW RESET
SD<0>                               6     18    FB6_2   45   I/O     I/O     STD  SLOW RESET
SA_HIGH<2>                          5     16    FB6_3   46   I/O     O       STD  SLOW RESET
SD<1>                               6     18    FB6_6   48   I/O     I/O     STD  SLOW RESET
SD<2>                               6     18    FB6_8   50   I/O     I/O     STD  SLOW RESET

Signal                              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                Pts   Inps          No.  Type    Use     Mode Rate State
SD<7>                               6     18    FB6_11  52   I/O     I/O     STD  SLOW RESET
REO                                 6     14    FB6_14  54   I/O     O       STD  SLOW 
SA_LOW<3>                           5     16    FB6_17  56   I/O     O       STD  SLOW RESET

** 21 Buried Nodes **

Signal                              Total Total Loc     Pwr  Reg Init
Name                                Pts   Inps          Mode State
ITRP_STA<2>                         2     2     FB2_14  STD  RESET
ITRP_STA<1>                         2     2     FB2_16  STD  RESET
ITRP_STA<0>                         2     2     FB2_18  STD  RESET
GATE_ITRP                           5     16    FB3_10  STD  RESET
RESET_CTL                           5     16    FB3_12  STD  RESET
XLXI_395/XLXN_43                    3     10    FB3_13  STD  RESET
XLXN_409/XLXN_409_SETF__$INT        1     2     FB3_15  STD  
XLXN_428/XLXN_428_SETF__$INT        1     2     FB3_18  STD  
ITRP_STA<3>                         2     2     FB4_18  STD  RESET
ITRP_STA<3>/ITRP_STA<3>_RSTF__$INT  1     2     FB5_1   STD  
ITRP_STA<2>/ITRP_STA<2>_RSTF__$INT  1     2     FB5_15  STD  
INTE_D                              5     16    FB5_18  STD  RESET
ITRP_STA<1>/ITRP_STA<1>_RSTF__$INT  1     2     FB6_5   STD  
ITRP_STA<0>/ITRP_STA<0>_RSTF__$INT  1     2     FB6_7   STD  
DH3                                 3     10    FB6_9   STD  RESET
DH2                                 3     10    FB6_10  STD  RESET
DH1                                 3     10    FB6_12  STD  RESET
DH0                                 3     10    FB6_13  STD  RESET
INTE_C                              5     16    FB6_15  STD  RESET
INTE_B                              5     16    FB6_16  STD  RESET
INTE_A                              5     16    FB6_18  STD  RESET

** 16 Inputs **

Signal                              Loc     Pin  Pin     Pin     
Name                                        No.  Type    Use     
CSEL                                FB1_6   4    I/O     I
INT_D                               FB1_9   6    I/O     I
DIOWn                               FB1_12  9    GCK/I/O GCK/I
DIORn                               FB1_14  10   GCK/I/O I
REI                                 FB2_8   76   GTS/I/O GTS
DMARQ                               FB2_14  81   I/O     I
DA0                                 FB2_16  83   I/O     I
INT_A                               FB3_6   18   I/O     I
DMACKn                              FB4_9   65   I/O     I
INT_C                               FB4_12  67   I/O     I
CS0n                                FB4_15  69   I/O     I
DA2                                 FB5_9   37   I/O     I
INT_B                               FB5_12  40   I/O     I
CS1n                                FB6_5   47   I/O     I
DA1                                 FB6_12  53   I/O     I
RESETn                              FB6_15  55   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               23/13
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/1   4     FB1_1         (b)     (b)
SD<4>                 6       1<-   0   0     FB1_2   1     I/O     I/O
IOWn                  1       0     0   4     FB1_3   2     I/O     O
(unused)              0       0   \/1   4     FB1_4         (b)     (b)
SD<5>                 6       1<-   0   0     FB1_5   3     I/O     I/O
(unused)              0       0     0   5     FB1_6   4     I/O     I
(unused)              0       0   \/1   4     FB1_7         (b)     (b)
SD<6>                 6       1<-   0   0     FB1_8   5     I/O     I/O
(unused)              0       0     0   5     FB1_9   6     I/O     I
(unused)              0       0     0   5     FB1_10        (b)     
AEN                   5       0     0   0     FB1_11  7     I/O     O
(unused)              0       0     0   5     FB1_12  9     GCK/I/O GCK/I
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  10    GCK/I/O I
(unused)              0       0     0   5     FB1_15  11    I/O     
(unused)              0       0     0   5     FB1_16  12    GCK/I/O 
SELECTEDn             2       0     0   3     FB1_17  13    I/O     O
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: DA0                   9: ISA_WR_DATA<5>.LFBK  17: DMARQ 
  2: DA1                  10: ISA_WR_DATA<6>.LFBK  18: CS0n 
  3: DA2                  11: WR_STATE_1n          19: XLXI_395/XLXN_43 
  4: DH0                  12: WR_STATE_2n          20: RESETn 
  5: DH1                  13: DD<4>.PIN            21: DMACKn 
  6: DH2                  14: DD<5>.PIN            22: CS1n 
  7: DH3                  15: DD<6>.PIN            23: XLXN_413.LFBK 
  8: ISA_WR_DATA<4>.LFBK  16: CSEL                

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SD<4>                XXXXXXXX..XXX..XXXXXXX.................. 18      18
IOWn                 ..........XX............................ 2       2
SD<5>                XXXXXXX.X.XX.X.XXXXXXX.................. 18      18
SD<6>                XXXXXXX..XXX..XXXXXXXX.................. 18      18
AEN                  XXXXXXX.......XXXXXXXXX................. 16      16
SELECTEDn            ...............X..X..................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
SA_LOW<0>             5       0     0   0     FB2_2   71    I/O     O
SA_LOW<1>             5       0     0   0     FB2_3   72    I/O     O
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   74    GSR/I/O 
SA_LOW<2>             5       0     0   0     FB2_6   75    I/O     O
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   76    GTS/I/O GTS
(unused)              0       0     0   5     FB2_9   77    GTS/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
SA_LOW<7>             5       0     0   0     FB2_11  79    I/O     O
SA_HIGH<0>            5       0     0   0     FB2_12  80    I/O     O
(unused)              0       0     0   5     FB2_13        (b)     
ITRP_STA<2>           2       0     0   3     FB2_14  81    I/O     I
SA_HIGH<1>            5       0     0   0     FB2_15  82    I/O     O
ITRP_STA<1>           2       0     0   3     FB2_16  83    I/O     I
SA_HIGH<7>            5       0     0   0     FB2_17  84    I/O     O
ITRP_STA<0>           2       0     0   3     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0                                 12: DD<1>.PIN         22: INT_A 
  2: DA1                                 13: DD<2>.PIN         23: INT_B 
  3: DA2                                 14: DD<7>.PIN         24: INT_C 
  4: DH0                                 15: CSEL              25: XLXN_48<0>.LFBK 
  5: DH1                                 16: DMARQ             26: XLXN_48<1>.LFBK 
  6: DH2                                 17: CS0n              27: XLXN_48<2>.LFBK 
  7: DH3                                 18: XLXI_395/XLXN_43  28: XLXN_48<7>.LFBK 
  8: ITRP_STA<0>/ITRP_STA<0>_RSTF__$INT  19: RESETn            29: XLXN_49<0>.LFBK 
  9: ITRP_STA<1>/ITRP_STA<1>_RSTF__$INT  20: DMACKn            30: XLXN_49<1>.LFBK 
 10: ITRP_STA<2>/ITRP_STA<2>_RSTF__$INT  21: CS1n              31: XLXN_49<7>.LFBK 
 11: DD<0>.PIN                          

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SA_LOW<0>            XXXXXXX...X...XXXXXXX...X............... 16      16
SA_LOW<1>            XXXXXXX....X..XXXXXXX....X.............. 16      16
SA_LOW<2>            XXXXXXX.....X.XXXXXXX.....X............. 16      16
SA_LOW<7>            XXXXXXX......XXXXXXXX......X............ 16      16
SA_HIGH<0>           XXXXXXX...X...XXXXXXX.......X........... 16      16
ITRP_STA<2>          .........X.............X................ 2       2
SA_HIGH<1>           XXXXXXX....X..XXXXXXX........X.......... 16      16
ITRP_STA<1>          ........X.............X................. 2       2
SA_HIGH<7>           XXXXXXX......XXXXXXXX.........X......... 16      16
ITRP_STA<0>          .......X.............X.................. 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB3_1         (b)     (b)
DD<2>                16      11<-   0   0     FB3_2   14    I/O     I/O
INTRQ                 2       0   /\3   0     FB3_3   15    I/O     O
(unused)              0       0   \/5   0     FB3_4         (b)     (b)
DD<3>                16      11<-   0   0     FB3_5   17    I/O     I/O
(unused)              0       0   /\5   0     FB3_6   18    I/O     I
(unused)              0       0   /\1   4     FB3_7         (b)     (b)
DD<5>                 4       0     0   1     FB3_8   19    I/O     I/O
ISA_RESET             1       0     0   4     FB3_9   20    I/O     O
GATE_ITRP             5       0     0   0     FB3_10        (b)     (b)
DD<6>                 4       0     0   1     FB3_11  21    I/O     I/O
RESET_CTL             5       0     0   0     FB3_12  23    I/O     (b)
XLXI_395/XLXN_43      3       0     0   2     FB3_13        (b)     (b)
DD<7>                 4       0     0   1     FB3_14  24    I/O     I/O
XLXN_409/XLXN_409_SETF__$INT
                      1       0     0   4     FB3_15  25    I/O     (b)
IORn                  4       0     0   1     FB3_16  26    I/O     O
RD_STATEn             4       0     0   1     FB3_17  31    I/O     O
XLXN_428/XLXN_428_SETF__$INT
                      1       0   \/3   1     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0               12: ITRP_STA<3>            22: RESETn 
  2: DA1               13: RESET_CTL.LFBK         23: DMACKn 
  3: DA2               14: DIOWn                  24: CS1n 
  4: DH0               15: DD<4>.PIN              25: SD<2>.PIN 
  5: DH1               16: DD<7>.PIN              26: SD<3>.PIN 
  6: DH2               17: DIORn                  27: SD<5>.PIN 
  7: DH3               18: CSEL                   28: SD<6>.PIN 
  8: GATE_ITRP.LFBK    19: DMARQ                  29: SD<7>.PIN 
  9: ITRP_STA<0>       20: CS0n                   30: XLXN_409.LFBK 
 10: ITRP_STA<1>       21: XLXI_395/XLXN_43.LFBK  31: XLXN_409/XLXN_409_SETF__$INT.LFBK 
 11: ITRP_STA<2>      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DD<2>                XXXXXXX...X.....XXXXX.XXX............... 16      16
INTRQ                .......XXXXX............................ 5       5
DD<3>                XXXXXXX....X....XXXXX.XX.X.............. 16      16
DD<5>                XXXXXXX.........XXXXX.XX..X............. 15      15
ISA_RESET            ............X........X.................. 2       2
GATE_ITRP            XXXXXXXX.......X.XXXXXXX................ 16      16
DD<6>                XXXXXXX.........XXXXX.XX...X............ 15      15
RESET_CTL            XXXXXXX.....X.X..XXXXXXX................ 16      16
XLXI_395/XLXN_43     XXX...........X...XXXXXX................ 10      10
DD<7>                XXXXXXX.........XXXXX.XX....X........... 15      15
XLXN_409/XLXN_409_SETF__$INT 
                     .............X.......X.................. 2       2
IORn                 XXXXXXX.........XXXXX.XX.....XX......... 16      16
RD_STATEn            XXXXXXX.........XXXXX.XX.....XX......... 16      16
XLXN_428/XLXN_428_SETF__$INT 
                     ................X....X.................. 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               27/9
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
SA_LOW<4>             5       0     0   0     FB4_2   57    I/O     O
SA_HIGH<6>            5       0     0   0     FB4_3   58    I/O     O
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   61    I/O     
SA_LOW<5>             5       0     0   0     FB4_6   62    I/O     O
(unused)              0       0     0   5     FB4_7         (b)     
SA_LOW<6>             5       0     0   0     FB4_8   63    I/O     O
(unused)              0       0     0   5     FB4_9   65    I/O     I
(unused)              0       0     0   5     FB4_10        (b)     
SA_HIGH<3>            5       0     0   0     FB4_11  66    I/O     O
(unused)              0       0     0   5     FB4_12  67    I/O     I
(unused)              0       0     0   5     FB4_13        (b)     
SA_HIGH<4>            5       0     0   0     FB4_14  68    I/O     O
(unused)              0       0     0   5     FB4_15  69    I/O     I
(unused)              0       0     0   5     FB4_16        (b)     
SA_HIGH<5>            5       0     0   0     FB4_17  70    I/O     O
ITRP_STA<3>           2       0     0   3     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0                                 10: DD<4>.PIN         19: CS1n 
  2: DA1                                 11: DD<5>.PIN         20: INT_D 
  3: DA2                                 12: DD<6>.PIN         21: XLXN_48<4>.LFBK 
  4: DH0                                 13: CSEL              22: XLXN_48<5>.LFBK 
  5: DH1                                 14: DMARQ             23: XLXN_48<6>.LFBK 
  6: DH2                                 15: CS0n              24: XLXN_49<3>.LFBK 
  7: DH3                                 16: XLXI_395/XLXN_43  25: XLXN_49<4>.LFBK 
  8: ITRP_STA<3>/ITRP_STA<3>_RSTF__$INT  17: RESETn            26: XLXN_49<5>.LFBK 
  9: DD<3>.PIN                           18: DMACKn            27: XLXN_49<6>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SA_LOW<4>            XXXXXXX..X..XXXXXXX.X................... 16      16
SA_HIGH<6>           XXXXXXX....XXXXXXXX.......X............. 16      16
SA_LOW<5>            XXXXXXX...X.XXXXXXX..X.................. 16      16
SA_LOW<6>            XXXXXXX....XXXXXXXX...X................. 16      16
SA_HIGH<3>           XXXXXXX.X...XXXXXXX....X................ 16      16
SA_HIGH<4>           XXXXXXX..X..XXXXXXX.....X............... 16      16
SA_HIGH<5>           XXXXXXX...X.XXXXXXX......X.............. 16      16
ITRP_STA<3>          .......X...........X.................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ITRP_STA<3>/ITRP_STA<3>_RSTF__$INT
                      1       0   /\2   2     FB5_1         (b)     (b)
WR_STATE_2n           2       0     0   3     FB5_2   32    I/O     O
ITRPn                 1       0   \/1   3     FB5_3   33    I/O     O
(unused)              0       0   \/5   0     FB5_4         (b)     (b)
DD<1>                16      11<-   0   0     FB5_5   34    I/O     I/O
(unused)              0       0   /\5   0     FB5_6   35    I/O     (b)
(unused)              0       0   \/1   4     FB5_7         (b)     (b)
SD<3>                 6       1<-   0   0     FB5_8   36    I/O     I/O
(unused)              0       0     0   5     FB5_9   37    I/O     I
(unused)              0       0     0   5     FB5_10        (b)     
DD<4>                 4       0     0   1     FB5_11  39    I/O     I/O
(unused)              0       0     0   5     FB5_12  40    I/O     I
(unused)              0       0     0   5     FB5_13        (b)     
WR_STATE_1n           3       0     0   2     FB5_14  41    I/O     O
ITRP_STA<2>/ITRP_STA<2>_RSTF__$INT
                      1       0   \/4   0     FB5_15  43    I/O     (b)
(unused)              0       0   \/5   0     FB5_16        (b)     (b)
DD<0>                16      11<-   0   0     FB5_17  44    I/O     I/O
INTE_D                5       2<- /\2   0     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0                  11: ITRP_STA<0>       21: RESETn 
  2: DA1                  12: ITRP_STA<1>       22: DMACKn 
  3: DA2                  13: ITRP_STA<2>       23: CS1n 
  4: DH0                  14: ITRP_STA<3>       24: SD<0>.PIN 
  5: DH1                  15: DD<3>.PIN         25: SD<1>.PIN 
  6: DH2                  16: DIORn             26: SD<4>.PIN 
  7: DH3                  17: CSEL              27: XLXN_425.LFBK 
  8: INTE_C               18: DMARQ             28: XLXN_428.LFBK 
  9: INTE_D.LFBK          19: CS0n              29: XLXN_428/XLXN_428_SETF__$INT 
 10: ISA_WR_DATA<3>.LFBK  20: XLXI_395/XLXN_43 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ITRP_STA<3>/ITRP_STA<3>_RSTF__$INT 
                     ........X...........X................... 2       2
WR_STATE_2n          ..........................X.X........... 2       2
ITRPn                ..........XXXX.......................... 4       4
DD<1>                XXXXXXX....X...XXXXX.XX.X............... 16      16
SD<3>                XXXXXXX..X....X.XXXXXXX...XX............ 18      18
DD<4>                XXXXXXX........XXXXX.XX..X.............. 15      15
WR_STATE_1n          XXXXXXX.........XXXX.XX...X.X........... 15      15
ITRP_STA<2>/ITRP_STA<2>_RSTF__$INT 
                     .......X............X................... 2       2
DD<0>                XXXXXXX...X....XXXXX.XXX................ 16      16
INTE_D               XXXXXXX.X.....X.XXXXXXX................. 16      16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/1   4     FB6_1         (b)     (b)
SD<0>                 6       1<-   0   0     FB6_2   45    I/O     I/O
SA_HIGH<2>            5       0     0   0     FB6_3   46    I/O     O
(unused)              0       0     0   5     FB6_4         (b)     
ITRP_STA<1>/ITRP_STA<1>_RSTF__$INT
                      1       0   \/1   3     FB6_5   47    I/O     I
SD<1>                 6       1<-   0   0     FB6_6   48    I/O     I/O
ITRP_STA<0>/ITRP_STA<0>_RSTF__$INT
                      1       0   \/1   3     FB6_7         (b)     (b)
SD<2>                 6       1<-   0   0     FB6_8   50    I/O     I/O
DH3                   3       0     0   2     FB6_9   51    I/O     (b)
DH2                   3       0   \/1   1     FB6_10        (b)     (b)
SD<7>                 6       1<-   0   0     FB6_11  52    I/O     I/O
DH1                   3       0     0   2     FB6_12  53    I/O     I
DH0                   3       0   \/1   1     FB6_13        (b)     (b)
REO                   6       1<-   0   0     FB6_14  54    I/O     O
INTE_C                5       0     0   0     FB6_15  55    I/O     I
INTE_B                5       0     0   0     FB6_16        (b)     (b)
SA_LOW<3>             5       0     0   0     FB6_17  56    I/O     O
INTE_A                5       0     0   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DA0                  12: ISA_WR_DATA<1>.LFBK  22: DIORn 
  2: DA1                  13: ISA_WR_DATA<2>.LFBK  23: CSEL 
  3: DA2                  14: ISA_WR_DATA<7>.LFBK  24: DMARQ 
  4: DH0.LFBK             15: WR_STATE_1n          25: CS0n 
  5: DH1.LFBK             16: WR_STATE_2n          26: XLXI_395/XLXN_43 
  6: DH2.LFBK             17: DD<0>.PIN            27: RESETn 
  7: DH3.LFBK             18: DD<1>.PIN            28: DMACKn 
  8: INTE_A.LFBK          19: DD<2>.PIN            29: CS1n 
  9: INTE_B.LFBK          20: DD<3>.PIN            30: XLXN_48<3>.LFBK 
 10: INTE_C.LFBK          21: DD<7>.PIN            31: XLXN_49<2>.LFBK 
 11: ISA_WR_DATA<0>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SD<0>                XXXXXXX...X...XXX.....XXXXXXX........... 18      18
SA_HIGH<2>           XXXXXXX...........X...XXXXXXX.X......... 16      16
ITRP_STA<1>/ITRP_STA<1>_RSTF__$INT 
                     ........X.................X............. 2       2
SD<1>                XXXXXXX....X..XX.X....XXXXXXX........... 18      18
ITRP_STA<0>/ITRP_STA<0>_RSTF__$INT 
                     .......X..................X............. 2       2
SD<2>                XXXXXXX.....X.XX..X...XXXXXXX........... 18      18
DH3                  XXX...X............X...XX.XXX........... 10      10
DH2                  XXX..X............X....XX.XXX........... 10      10
SD<7>                XXXXXXX......XXX....X.XXXXXXX........... 18      18
DH1                  XXX.X............X.....XX.XXX........... 10      10
DH0                  XXXX............X......XX.XXX........... 10      10
REO                  XXXXXXX..............XXXXX.XX........... 14      14
INTE_C               XXXXXXX..X........X...XXXXXXX........... 16      16
INTE_B               XXXXXXX.X........X....XXXXXXX........... 16      16
SA_LOW<3>            XXXXXXX............X..XXXXXXXX.......... 16      16
INTE_A               XXXXXXXX........X.....XXXXXXX........... 16      16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_AEN: FTCPE port map (AEN,AEN_T,DIOWn,'0',NOT RESETn);
AEN_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(6).PIN AND CSEL AND XLXN_413.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND CSEL AND NOT XLXN_413.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(6).PIN AND NOT CSEL AND XLXN_413.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND NOT CSEL AND NOT XLXN_413.LFBK));

FDCPE_DD0: FDCPE port map (DD_I(0),DD(0),NOT DIORn,'0','0');
DD(0) <= ((EXP10_.EXP)
	OR (INTE_D.EXP)
	OR (NOT DMACKn AND SD(0).PIN)
	OR (NOT CS1n AND SD(0).PIN)
	OR (DMARQ AND SD(0).PIN)
	OR (CS0n AND SD(0).PIN));

FDCPE_DD1: FDCPE port map (DD_I(1),DD(1),NOT DIORn,'0','0');
DD(1) <= ((EXP7_.EXP)
	OR (EXP8_.EXP)
	OR (NOT DMACKn AND SD(1).PIN)
	OR (NOT CS1n AND SD(1).PIN)
	OR (DMARQ AND SD(1).PIN)
	OR (CS0n AND SD(1).PIN));

FDCPE_DD2: FDCPE port map (DD_I(2),DD(2),NOT DIORn,'0','0');
DD(2) <= ((EXP3_.EXP)
	OR (XLXN_223.EXP)
	OR (NOT DMACKn AND SD(2).PIN)
	OR (NOT CS1n AND SD(2).PIN)
	OR (DMARQ AND SD(2).PIN)
	OR (CS0n AND SD(2).PIN));

FDCPE_DD3: FDCPE port map (DD_I(3),DD(3),NOT DIORn,'0','0');
DD(3) <= ((EXP4_.EXP)
	OR (EXP5_.EXP)
	OR (NOT DMACKn AND SD(3).PIN)
	OR (NOT CS1n AND SD(3).PIN)
	OR (DMARQ AND SD(3).PIN)
	OR (CS0n AND SD(3).PIN));

FDCPE_DD4: FDCPE port map (DD_I(4),DD(4),NOT DIORn,'0','0');
DD(4) <= ((NOT SD(4).PIN)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	CSEL)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT CSEL));

FDCPE_DD5: FDCPE port map (DD_I(5),DD(5),NOT DIORn,'0','0');
DD(5) <= ((NOT SD(5).PIN)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND CSEL AND 
	XLXI_395/XLXN_43.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK));

FDCPE_DD6: FDCPE port map (DD_I(6),DD(6),NOT DIORn,'0','0');
DD(6) <= ((NOT SD(6).PIN)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND CSEL AND 
	XLXI_395/XLXN_43.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK));

FDCPE_DD7: FDCPE port map (DD_I(7),DD(7),NOT DIORn,'0','0');
DD(7) <= ((NOT SD(7).PIN)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND CSEL AND 
	XLXI_395/XLXN_43.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK));

FTCPE_DH0: FTCPE port map (DH0,DH0_T,DIOWn,NOT RESETn,'0');
DH0_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(0).PIN AND NOT DH0.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(0).PIN AND DH0.LFBK));

FTCPE_DH1: FTCPE port map (DH1,DH1_T,DIOWn,NOT RESETn,'0');
DH1_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(1).PIN AND NOT DH1.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(1).PIN AND DH1.LFBK));

FTCPE_DH2: FTCPE port map (DH2,DH2_T,DIOWn,NOT RESETn,'0');
DH2_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(2).PIN AND NOT DH2.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(2).PIN AND DH2.LFBK));

FTCPE_DH3: FTCPE port map (DH3,DH3_T,DIOWn,NOT RESETn,'0');
DH3_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(3).PIN AND NOT DH3.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(3).PIN AND DH3.LFBK));

























FTCPE_GATE_ITRP: FTCPE port map (GATE_ITRP,GATE_ITRP_T,DIOWn,NOT RESETn,'0');
GATE_ITRP_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND DD(7).PIN AND CSEL AND 
	NOT GATE_ITRP.LFBK AND XLXI_395/XLXN_43.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND DD(7).PIN AND NOT CSEL AND 
	NOT GATE_ITRP.LFBK AND NOT XLXI_395/XLXN_43.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT DD(7).PIN AND CSEL AND 
	GATE_ITRP.LFBK AND XLXI_395/XLXN_43.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT DD(7).PIN AND NOT CSEL AND 
	GATE_ITRP.LFBK AND NOT XLXI_395/XLXN_43.LFBK));

FTCPE_INTE_A: FTCPE port map (INTE_A,INTE_A_T,DIOWn,NOT RESETn,'0');
INTE_A_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(0).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_A.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(0).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_A.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(0).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_A.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND NOT DD(0).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_A.LFBK));

FTCPE_INTE_B: FTCPE port map (INTE_B,INTE_B_T,DIOWn,NOT RESETn,'0');
INTE_B_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(1).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_B.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(1).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_B.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(1).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_B.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND NOT DD(1).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_B.LFBK));

FTCPE_INTE_C: FTCPE port map (INTE_C,INTE_C_T,DIOWn,NOT RESETn,'0');
INTE_C_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_C.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_C.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT INTE_C.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND NOT DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND INTE_C.LFBK));

FTCPE_INTE_D: FTCPE port map (INTE_D,INTE_D_T,DIOWn,NOT RESETn,'0');
INTE_D_T <= ((ITRP_STA(3)/ITRP_STA(3)_RSTF__$INT.EXP)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(3).PIN AND CSEL AND NOT INTE_D.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(3).PIN AND NOT CSEL AND NOT INTE_D.LFBK));


INTRQ_I <= NOT ((NOT ITRP_STA(0) AND NOT ITRP_STA(1) AND NOT ITRP_STA(2) AND 
	NOT ITRP_STA(3)));
INTRQ <= INTRQ_I when INTRQ_OE = '1' else 'Z';
INTRQ_OE <= GATE_ITRP.LFBK;

FDCPE_IORn: FDCPE port map (IORn,IORn_D,DIORn,'0',NOT XLXN_409/XLXN_409_SETF__$INT.LFBK);
IORn_D <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND CSEL AND 
	XLXI_395/XLXN_43.LFBK AND XLXN_409.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK AND XLXN_409.LFBK));


IOWn <= NOT ((NOT WR_STATE_1n AND NOT WR_STATE_2n));


ISA_RESET <= NOT ((RESETn AND NOT RESET_CTL.LFBK));


ITRP_STA(0)/ITRP_STA(0)_RSTF__$INT <= (RESETn AND INTE_A.LFBK);

FDCPE_ITRP_STA0: FDCPE port map (ITRP_STA(0),'1',INT_A,NOT ITRP_STA(0)/ITRP_STA(0)_RSTF__$INT,'0');


ITRP_STA(1)/ITRP_STA(1)_RSTF__$INT <= (RESETn AND INTE_B.LFBK);

FDCPE_ITRP_STA1: FDCPE port map (ITRP_STA(1),'1',INT_B,NOT ITRP_STA(1)/ITRP_STA(1)_RSTF__$INT,'0');


ITRP_STA(2)/ITRP_STA(2)_RSTF__$INT <= (RESETn AND INTE_C);

FDCPE_ITRP_STA2: FDCPE port map (ITRP_STA(2),'1',INT_C,NOT ITRP_STA(2)/ITRP_STA(2)_RSTF__$INT,'0');

FDCPE_ITRP_STA3: FDCPE port map (ITRP_STA(3),'1',INT_D,NOT ITRP_STA(3)/ITRP_STA(3)_RSTF__$INT,'0');


ITRP_STA(3)/ITRP_STA(3)_RSTF__$INT <= (RESETn AND INTE_D.LFBK);


ITRPn <= (NOT ITRP_STA(0) AND NOT ITRP_STA(1) AND NOT ITRP_STA(2) AND 
	NOT ITRP_STA(3));

FDCPE_RD_STATEn: FDCPE port map (RD_STATEn,RD_STATEn_D,DIORn,'0',NOT XLXN_409/XLXN_409_SETF__$INT.LFBK);
RD_STATEn_D <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND CSEL AND 
	XLXI_395/XLXN_43.LFBK AND XLXN_409.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK AND XLXN_409.LFBK));


REO <= ((DH0.EXP)
	OR (NOT DIORn AND DA0 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND 
	XLXI_395/XLXN_43 AND CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DIORn AND DA0 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND 
	NOT XLXI_395/XLXN_43 AND NOT CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DIORn AND NOT DA1 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND 
	XLXI_395/XLXN_43 AND CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DIORn AND NOT DA1 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND 
	NOT XLXI_395/XLXN_43 AND NOT CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK)
	OR (NOT DIORn AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND NOT CS0n AND 
	XLXI_395/XLXN_43 AND CSEL AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND 
	DH3.LFBK));

FTCPE_RESET_CTL: FTCPE port map (RESET_CTL,RESET_CTL_T,DIOWn,NOT RESETn,'0');
RESET_CTL_T <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND DD(4).PIN AND CSEL AND 
	XLXI_395/XLXN_43.LFBK AND NOT RESET_CTL.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND DD(4).PIN AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK AND NOT RESET_CTL.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT DD(4).PIN AND CSEL AND 
	XLXI_395/XLXN_43.LFBK AND RESET_CTL.LFBK)
	OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT DD(4).PIN AND NOT CSEL AND 
	NOT XLXI_395/XLXN_43.LFBK AND RESET_CTL.LFBK));

FTCPE_SA_HIGH0: FTCPE port map (SA_HIGH(0),SA_HIGH_T(0),DIOWn,NOT RESETn,'0');
SA_HIGH_T(0) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(0).PIN AND CSEL AND NOT XLXN_49(0).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(0).PIN AND CSEL AND XLXN_49(0).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(0).PIN AND NOT CSEL AND NOT XLXN_49(0).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(0).PIN AND NOT CSEL AND XLXN_49(0).LFBK));

FTCPE_SA_HIGH1: FTCPE port map (SA_HIGH(1),SA_HIGH_T(1),DIOWn,NOT RESETn,'0');
SA_HIGH_T(1) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(1).PIN AND CSEL AND NOT XLXN_49(1).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(1).PIN AND CSEL AND XLXN_49(1).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(1).PIN AND NOT CSEL AND NOT XLXN_49(1).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(1).PIN AND NOT CSEL AND XLXN_49(1).LFBK));

FTCPE_SA_HIGH2: FTCPE port map (SA_HIGH(2),SA_HIGH_T(2),DIOWn,NOT RESETn,'0');
SA_HIGH_T(2) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_49(2).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(2).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_49(2).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_49(2).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND NOT DD(2).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_49(2).LFBK));

FTCPE_SA_HIGH3: FTCPE port map (SA_HIGH(3),SA_HIGH_T(3),DIOWn,NOT RESETn,'0');
SA_HIGH_T(3) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(3).PIN AND CSEL AND NOT XLXN_49(3).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(3).PIN AND CSEL AND XLXN_49(3).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(3).PIN AND NOT CSEL AND NOT XLXN_49(3).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(3).PIN AND NOT CSEL AND XLXN_49(3).LFBK));

FTCPE_SA_HIGH4: FTCPE port map (SA_HIGH(4),SA_HIGH_T(4),DIOWn,NOT RESETn,'0');
SA_HIGH_T(4) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(4).PIN AND CSEL AND NOT XLXN_49(4).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(4).PIN AND CSEL AND XLXN_49(4).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(4).PIN AND NOT CSEL AND NOT XLXN_49(4).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(4).PIN AND NOT CSEL AND XLXN_49(4).LFBK));

FTCPE_SA_HIGH5: FTCPE port map (SA_HIGH(5),SA_HIGH_T(5),DIOWn,NOT RESETn,'0');
SA_HIGH_T(5) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(5).PIN AND CSEL AND NOT XLXN_49(5).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(5).PIN AND CSEL AND XLXN_49(5).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(5).PIN AND NOT CSEL AND NOT XLXN_49(5).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(5).PIN AND NOT CSEL AND XLXN_49(5).LFBK));

FTCPE_SA_HIGH6: FTCPE port map (SA_HIGH(6),SA_HIGH_T(6),DIOWn,NOT RESETn,'0');
SA_HIGH_T(6) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(6).PIN AND CSEL AND NOT XLXN_49(6).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND CSEL AND XLXN_49(6).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(6).PIN AND NOT CSEL AND NOT XLXN_49(6).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND NOT CSEL AND XLXN_49(6).LFBK));

FTCPE_SA_HIGH7: FTCPE port map (SA_HIGH(7),SA_HIGH_T(7),DIOWn,NOT RESETn,'0');
SA_HIGH_T(7) <= ((DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(7).PIN AND CSEL AND NOT XLXN_49(7).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(7).PIN AND CSEL AND XLXN_49(7).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(7).PIN AND NOT CSEL AND NOT XLXN_49(7).LFBK)
	OR (DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(7).PIN AND NOT CSEL AND XLXN_49(7).LFBK));

FTCPE_SA_LOW0: FTCPE port map (SA_LOW(0),SA_LOW_T(0),DIOWn,NOT RESETn,'0');
SA_LOW_T(0) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(0).PIN AND CSEL AND NOT XLXN_48(0).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(0).PIN AND CSEL AND XLXN_48(0).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(0).PIN AND NOT CSEL AND NOT XLXN_48(0).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(0).PIN AND NOT CSEL AND XLXN_48(0).LFBK));

FTCPE_SA_LOW1: FTCPE port map (SA_LOW(1),SA_LOW_T(1),DIOWn,NOT RESETn,'0');
SA_LOW_T(1) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(1).PIN AND CSEL AND NOT XLXN_48(1).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(1).PIN AND CSEL AND XLXN_48(1).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(1).PIN AND NOT CSEL AND NOT XLXN_48(1).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(1).PIN AND NOT CSEL AND XLXN_48(1).LFBK));

FTCPE_SA_LOW2: FTCPE port map (SA_LOW(2),SA_LOW_T(2),DIOWn,NOT RESETn,'0');
SA_LOW_T(2) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(2).PIN AND CSEL AND NOT XLXN_48(2).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(2).PIN AND CSEL AND XLXN_48(2).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(2).PIN AND NOT CSEL AND NOT XLXN_48(2).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(2).PIN AND NOT CSEL AND XLXN_48(2).LFBK));

FTCPE_SA_LOW3: FTCPE port map (SA_LOW(3),SA_LOW_T(3),DIOWn,NOT RESETn,'0');
SA_LOW_T(3) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(3).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_48(3).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(3).PIN AND CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_48(3).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(3).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND NOT XLXN_48(3).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND NOT DD(3).PIN AND NOT CSEL AND NOT DH0.LFBK AND 
	NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND XLXN_48(3).LFBK));

FTCPE_SA_LOW4: FTCPE port map (SA_LOW(4),SA_LOW_T(4),DIOWn,NOT RESETn,'0');
SA_LOW_T(4) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(4).PIN AND CSEL AND NOT XLXN_48(4).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(4).PIN AND CSEL AND XLXN_48(4).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(4).PIN AND NOT CSEL AND NOT XLXN_48(4).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(4).PIN AND NOT CSEL AND XLXN_48(4).LFBK));

FTCPE_SA_LOW5: FTCPE port map (SA_LOW(5),SA_LOW_T(5),DIOWn,NOT RESETn,'0');
SA_LOW_T(5) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(5).PIN AND CSEL AND NOT XLXN_48(5).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(5).PIN AND CSEL AND XLXN_48(5).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(5).PIN AND NOT CSEL AND NOT XLXN_48(5).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(5).PIN AND NOT CSEL AND XLXN_48(5).LFBK));

FTCPE_SA_LOW6: FTCPE port map (SA_LOW(6),SA_LOW_T(6),DIOWn,NOT RESETn,'0');
SA_LOW_T(6) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(6).PIN AND CSEL AND NOT XLXN_48(6).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND CSEL AND XLXN_48(6).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(6).PIN AND NOT CSEL AND NOT XLXN_48(6).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND NOT CSEL AND XLXN_48(6).LFBK));

FTCPE_SA_LOW7: FTCPE port map (SA_LOW(7),SA_LOW_T(7),DIOWn,NOT RESETn,'0');
SA_LOW_T(7) <= ((NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(7).PIN AND CSEL AND NOT XLXN_48(7).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(7).PIN AND CSEL AND XLXN_48(7).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(7).PIN AND NOT CSEL AND NOT XLXN_48(7).LFBK)
	OR (NOT DA0 AND DA1 AND NOT DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT DD(7).PIN AND NOT CSEL AND XLXN_48(7).LFBK));

FTCPE_SD0: FTCPE port map (SD_I(0),SD_T(0),DIOWn,NOT RESETn,'0');
SD_T(0) <= ((EXP11_.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(0).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT ISA_WR_DATA(0).LFBK AND NOT DH0.LFBK AND NOT DH1.LFBK AND 
	DH2.LFBK AND DH3.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(0).PIN AND CSEL AND 
	NOT WR_STATE_1n AND ISA_WR_DATA(0).LFBK AND NOT DH0.LFBK AND NOT DH1.LFBK AND 
	DH2.LFBK AND DH3.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(0).PIN AND NOT CSEL AND 
	NOT WR_STATE_1n AND NOT ISA_WR_DATA(0).LFBK AND NOT DH0.LFBK AND NOT DH1.LFBK AND 
	DH2.LFBK AND DH3.LFBK));
SD(0) <= SD_I(0) when SD_OE(0) = '1' else 'Z';
SD_OE(0) <= NOT WR_STATE_2n;

FTCPE_SD1: FTCPE port map (SD_I(1),SD_T(1),DIOWn,NOT RESETn,'0');
SD_T(1) <= ((ITRP_STA(1)/ITRP_STA(1)_RSTF__$INT.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(1).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	NOT ISA_WR_DATA(1).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(1).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	ISA_WR_DATA(1).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(1).PIN AND NOT CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	NOT ISA_WR_DATA(1).LFBK));
SD(1) <= SD_I(1) when SD_OE(1) = '1' else 'Z';
SD_OE(1) <= NOT WR_STATE_2n;

FTCPE_SD2: FTCPE port map (SD_I(2),SD_T(2),DIOWn,NOT RESETn,'0');
SD_T(2) <= ((ITRP_STA(0)/ITRP_STA(0)_RSTF__$INT.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(2).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	NOT ISA_WR_DATA(2).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(2).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	ISA_WR_DATA(2).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(2).PIN AND NOT CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	NOT ISA_WR_DATA(2).LFBK));
SD(2) <= SD_I(2) when SD_OE(2) = '1' else 'Z';
SD_OE(2) <= NOT WR_STATE_2n;

FTCPE_SD3: FTCPE port map (SD_I(3),SD_T(3),DIOWn,NOT RESETn,'0');
SD_T(3) <= ((EXP9_.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(3).PIN AND CSEL AND NOT ISA_WR_DATA(3).LFBK AND NOT XLXN_425.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(3).PIN AND CSEL AND ISA_WR_DATA(3).LFBK AND NOT XLXN_425.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(3).PIN AND NOT CSEL AND NOT ISA_WR_DATA(3).LFBK AND NOT XLXN_425.LFBK));
SD(3) <= SD_I(3) when SD_OE(3) = '1' else 'Z';
SD_OE(3) <= NOT XLXN_428.LFBK;

FTCPE_SD4: FTCPE port map (SD_I(4),SD_T(4),DIOWn,NOT RESETn,'0');
SD_T(4) <= ((EXP0_.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(4).PIN AND CSEL AND NOT WR_STATE_1n AND NOT ISA_WR_DATA(4).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(4).PIN AND CSEL AND NOT WR_STATE_1n AND ISA_WR_DATA(4).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(4).PIN AND NOT CSEL AND NOT WR_STATE_1n AND NOT ISA_WR_DATA(4).LFBK));
SD(4) <= SD_I(4) when SD_OE(4) = '1' else 'Z';
SD_OE(4) <= NOT WR_STATE_2n;

FTCPE_SD5: FTCPE port map (SD_I(5),SD_T(5),DIOWn,NOT RESETn,'0');
SD_T(5) <= ((EXP1_.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(5).PIN AND CSEL AND NOT WR_STATE_1n AND NOT ISA_WR_DATA(5).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(5).PIN AND CSEL AND NOT WR_STATE_1n AND ISA_WR_DATA(5).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(5).PIN AND NOT CSEL AND NOT WR_STATE_1n AND NOT ISA_WR_DATA(5).LFBK));
SD(5) <= SD_I(5) when SD_OE(5) = '1' else 'Z';
SD_OE(5) <= NOT WR_STATE_2n;

FTCPE_SD6: FTCPE port map (SD_I(6),SD_T(6),DIOWn,NOT RESETn,'0');
SD_T(6) <= ((EXP2_.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	DD(6).PIN AND CSEL AND NOT WR_STATE_1n AND NOT ISA_WR_DATA(6).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	NOT DD(6).PIN AND CSEL AND NOT WR_STATE_1n AND ISA_WR_DATA(6).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	DD(6).PIN AND NOT CSEL AND NOT WR_STATE_1n AND NOT ISA_WR_DATA(6).LFBK));
SD(6) <= SD_I(6) when SD_OE(6) = '1' else 'Z';
SD_OE(6) <= NOT WR_STATE_2n;

FTCPE_SD7: FTCPE port map (SD_I(7),SD_T(7),DIOWn,NOT RESETn,'0');
SD_T(7) <= ((DH2.EXP)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND DD(7).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	NOT ISA_WR_DATA(7).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND XLXI_395/XLXN_43 AND NOT DD(7).PIN AND CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	ISA_WR_DATA(7).LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT XLXI_395/XLXN_43 AND DD(7).PIN AND NOT CSEL AND 
	NOT WR_STATE_1n AND NOT DH0.LFBK AND NOT DH1.LFBK AND DH2.LFBK AND DH3.LFBK AND 
	NOT ISA_WR_DATA(7).LFBK));
SD(7) <= SD_I(7) when SD_OE(7) = '1' else 'Z';
SD_OE(7) <= NOT WR_STATE_2n;


SELECTEDn <= XLXI_395/XLXN_43
	 XOR 
SELECTEDn <= CSEL;

FDCPE_WR_STATE_1n: FDCPE port map (WR_STATE_1n,WR_STATE_1n_D,NOT DIOWn,'0',NOT XLXN_428/XLXN_428_SETF__$INT);
WR_STATE_1n_D <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND XLXI_395/XLXN_43 AND 
	CSEL AND XLXN_425.LFBK)
	OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DH0 AND NOT DH1 AND DH2 AND DH3 AND NOT XLXI_395/XLXN_43 AND 
	NOT CSEL AND XLXN_425.LFBK));

FDCPE_WR_STATE_2n: FDCPE port map (WR_STATE_2n,XLXN_425.LFBK,DIOWn,'0',NOT XLXN_428/XLXN_428_SETF__$INT);

FTCPE_XLXI_395/XLXN_43: FTCPE port map (XLXI_395/XLXN_43,XLXI_395/XLXN_43_T,DIOWn,NOT RESETn,'0');
XLXI_395/XLXN_43_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND DD(4).PIN AND NOT XLXI_395/XLXN_43.LFBK)
	OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND 
	NOT CS0n AND NOT DD(4).PIN AND XLXI_395/XLXN_43.LFBK));


XLXN_409/XLXN_409_SETF__$INT <= (DIOWn AND RESETn);


XLXN_428/XLXN_428_SETF__$INT <= (RESETn AND DIORn);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


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  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
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 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 SD<4>                            43 PGND                          
  2 IOWn                             44 DD<0>                         
  3 SD<5>                            45 SD<0>                         
  4 CSEL                             46 SA_HIGH<2>                    
  5 SD<6>                            47 CS1n                          
  6 INT_D                            48 SD<1>                         
  7 AEN                              49 GND                           
  8 GND                              50 SD<2>                         
  9 DIOWn                            51 PGND                          
 10 DIORn                            52 SD<7>                         
 11 PGND                             53 DA1                           
 12 PGND                             54 REO                           
 13 SELECTEDn                        55 RESETn                        
 14 DD<2>                            56 SA_LOW<3>                     
 15 INTRQ                            57 SA_LOW<4>                     
 16 GND                              58 SA_HIGH<6>                    
 17 DD<3>                            59 TDO                           
 18 INT_A                            60 GND                           
 19 DD<5>                            61 PGND                          
 20 ISA_RESET                        62 SA_LOW<5>                     
 21 DD<6>                            63 SA_LOW<6>                     
 22 VCC                              64 VCC                           
 23 PGND                             65 DMACKn                        
 24 DD<7>                            66 SA_HIGH<3>                    
 25 PGND                             67 INT_C                         
 26 IORn                             68 SA_HIGH<4>                    
 27 GND                              69 CS0n                          
 28 TDI                              70 SA_HIGH<5>                    
 29 TMS                              71 SA_LOW<0>                     
 30 TCK                              72 SA_LOW<1>                     
 31 RD_STATEn                        73 VCC                           
 32 WR_STATE_2n                      74 PGND                          
 33 ITRPn                            75 SA_LOW<2>                     
 34 DD<1>                            76 REI                           
 35 PGND                             77 PGND                          
 36 SD<3>                            78 VCC                           
 37 DA2                              79 SA_LOW<7>                     
 38 VCC                              80 SA_HIGH<0>                    
 39 DD<4>                            81 DMARQ                         
 40 INT_B                            82 SA_HIGH<1>                    
 41 WR_STATE_1n                      83 DA0                           
 42 GND                              84 SA_HIGH<7>                    


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Ground on Unused IOs                        : ON
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25