Design Name | ata_port_05a1 |
Fitting Status | Successful |
Software Version | I.27 |
Device Used | XC95144-10-PQ100 |
Date | 11-18-2006, 5:56PM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
95/144 (66%) | 423/720 (59%) | 93/144 (65%) | 66/81 (82%) | 240/288 (84%) |
|
|
Signal mapped onto global clock net (GCK1) | DIOWn |
Signal mapped onto global clock net (GCK2) | /DIORn |
Signal mapped onto global output enable net (GTS3) | REI |
Signal mapped onto global output enable net (GSR) | /RESETn |
Macrocells in high performance mode (MCHP) | 95 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 95 |