Timing Report

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Design Name vollad_rtl
Device, Speed (SpeedFile Version) XC95108, -7 (3.0)
Date Created Sun Jan 10 11:50:30 2010
Created By Timing Report Generator: version J.33
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Pad to Pad Delay (tPD) 20.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 20.0 42 42
AUTO_TS_P2F 0.0 0.0 0 0
AUTO_TS_F2P 0.0 0.0 0 0


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A<2> to CO 0.000 20.000 -20.000
A<2> to S<3> 0.000 20.000 -20.000
B<0> to S<2> 0.000 20.000 -20.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 1

Data Sheet Report

Pad to Pad List

Source Pad Destination Pad Delay
A<2> CO 20.000
A<2> S<3> 20.000
B<0> S<2> 20.000
B<1> S<2> 20.000
B<2> CO 20.000
B<2> S<3> 20.000
CI S<2> 20.000
A<0> CO 19.000
A<0> S<2> 19.000
A<0> S<3> 19.000
A<1> CO 19.000
A<1> S<2> 19.000
A<1> S<3> 19.000
B<0> CO 19.000
B<0> S<3> 19.000
B<1> CO 19.000
B<1> S<3> 19.000
CI CO 19.000
CI S<3> 19.000
A<0> ZERO 9.500
A<1> ZERO 9.500
A<2> ZERO 9.500
A<3> ZERO 9.500
B<0> ZERO 9.500
B<1> ZERO 9.500
B<2> ZERO 9.500
B<3> ZERO 9.500
CI ZERO 9.500
B<0> S<1> 8.500
B<1> S<1> 8.500
CI S<1> 8.500
A<0> S<0> 7.500
A<0> S<1> 7.500
A<1> S<1> 7.500
A<2> S<2> 7.500
A<3> CO 7.500
A<3> S<3> 7.500
B<0> S<0> 7.500
B<2> S<2> 7.500
B<3> CO 7.500
B<3> S<3> 7.500
CI S<0> 7.500



Number of paths analyzed: 42
Number of Timing errors: 42
Analysis Completed: Sun Jan 10 11:50:30 2010