********** Mapped Logic ********** |
FDCPE_Q0: FDCPE port map (Q(0),Q_D(0),CLK,'0','0');
Q_D(0) <= ((NOT CLR AND PRE) OR (NOT CLR AND LOAD AND D(0)) OR (NOT CLR AND NOT LOAD AND LDN AND NOT D(0)) OR (NOT CLR AND NOT LOAD AND NOT LDN AND Q_0.LFBK)); |
FDCPE_Q1: FDCPE port map (Q(1),Q_D(1),CLK,'0','0');
Q_D(1) <= ((NOT CLR AND PRE) OR (NOT CLR AND LOAD AND D(1)) OR (NOT CLR AND NOT LOAD AND LDN AND NOT D(1)) OR (NOT CLR AND NOT LOAD AND NOT LDN AND Q_1.LFBK)); |
FDCPE_Q2: FDCPE port map (Q(2),Q_D(2),CLK,'0','0');
Q_D(2) <= ((NOT CLR AND PRE) OR (NOT CLR AND LOAD AND D(2)) OR (NOT CLR AND NOT LOAD AND LDN AND NOT D(2)) OR (NOT CLR AND NOT LOAD AND NOT LDN AND Q_2.LFBK)); |
FDCPE_Q3: FDCPE port map (Q(3),Q_D(3),CLK,'0','0');
Q_D(3) <= ((NOT CLR AND PRE) OR (NOT CLR AND LOAD AND D(3)) OR (NOT CLR AND NOT LOAD AND NOT D(3) AND LDN) OR (NOT CLR AND NOT LOAD AND NOT LDN AND Q_3.LFBK)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |