Design Name | reg_8_2 |
Device, Speed (SpeedFile Version) | XC95108, -7 (3.0) |
Date Created | Sun Jan 17 14:12:37 2010 |
Created By | Timing Report Generator: version J.33 |
Copyright | Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Min. Clock Period | 9.000 ns. |
Max. Clock Frequency (fSYSTEM) | 111.111 MHz. |
Limited by Cycle Time for C | |
Clock to Setup (tCYC) | 9.000 ns. |
Setup to Clock at the Pad (tSU) | 4.500 ns. |
Clock Pad to Output Pad Delay (tCO) | 4.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 9.0 | 36 | 36 |
AUTO_TS_P2P | 0.0 | 4.5 | 8 | 8 |
AUTO_TS_P2F | 0.0 | 6.0 | 41 | 41 |
AUTO_TS_F2P | 0.0 | 3.0 | 8 | 8 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
D_OUT<0>.Q to D_OUT<2>.D | 0.000 | 9.000 | -9.000 |
D_OUT<0>.Q to D_OUT<3>.D | 0.000 | 9.000 | -9.000 |
D_OUT<0>.Q to D_OUT<4>.D | 0.000 | 9.000 | -9.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
C to D_OUT<0> | 0.000 | 4.500 | -4.500 |
C to D_OUT<1> | 0.000 | 4.500 | -4.500 |
C to D_OUT<2> | 0.000 | 4.500 | -4.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CLR to D_OUT<0>.D | 0.000 | 6.000 | -6.000 |
CLR to D_OUT<1>.D | 0.000 | 6.000 | -6.000 |
CLR to D_OUT<2>.D | 0.000 | 6.000 | -6.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
D_OUT<0>.Q to D_OUT<0> | 0.000 | 3.000 | -3.000 |
D_OUT<1>.Q to D_OUT<1> | 0.000 | 3.000 | -3.000 |
D_OUT<2>.Q to D_OUT<2> | 0.000 | 3.000 | -3.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
C | 111.111 | Limited by Cycle Time for C |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
CLR | 4.500 | 0.000 |
CTB | 4.500 | 0.000 |
CTF | 4.500 | 0.000 |
D_IN<0> | 4.500 | 0.000 |
D_IN<1> | 4.500 | 0.000 |
D_IN<2> | 4.500 | 0.000 |
D_IN<3> | 4.500 | 0.000 |
D_IN<4> | 4.500 | 0.000 |
D_IN<5> | 4.500 | 0.000 |
D_IN<6> | 4.500 | 0.000 |
D_IN<7> | 4.500 | 0.000 |
LD | 4.500 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
D_OUT<0> | 4.500 |
D_OUT<1> | 4.500 |
D_OUT<2> | 4.500 |
D_OUT<3> | 4.500 |
D_OUT<4> | 4.500 |
D_OUT<5> | 4.500 |
D_OUT<6> | 4.500 |
D_OUT<7> | 4.500 |
Source | Destination | Delay |
---|---|---|
D_OUT<0>.Q | D_OUT<2>.D | 9.000 |
D_OUT<0>.Q | D_OUT<3>.D | 9.000 |
D_OUT<0>.Q | D_OUT<4>.D | 9.000 |
D_OUT<0>.Q | D_OUT<5>.D | 9.000 |
D_OUT<0>.Q | D_OUT<6>.D | 9.000 |
D_OUT<0>.Q | D_OUT<7>.D | 9.000 |
D_OUT<1>.Q | D_OUT<2>.D | 9.000 |
D_OUT<1>.Q | D_OUT<3>.D | 9.000 |
D_OUT<1>.Q | D_OUT<4>.D | 9.000 |
D_OUT<1>.Q | D_OUT<5>.D | 9.000 |
D_OUT<1>.Q | D_OUT<6>.D | 9.000 |
D_OUT<1>.Q | D_OUT<7>.D | 9.000 |
D_OUT<2>.Q | D_OUT<3>.D | 9.000 |
D_OUT<2>.Q | D_OUT<4>.D | 9.000 |
D_OUT<2>.Q | D_OUT<5>.D | 9.000 |
D_OUT<2>.Q | D_OUT<7>.D | 9.000 |
D_OUT<3>.Q | D_OUT<4>.D | 9.000 |
D_OUT<3>.Q | D_OUT<5>.D | 9.000 |
D_OUT<3>.Q | D_OUT<6>.D | 9.000 |
D_OUT<3>.Q | D_OUT<7>.D | 9.000 |
D_OUT<4>.Q | D_OUT<5>.D | 9.000 |
D_OUT<4>.Q | D_OUT<6>.D | 9.000 |
D_OUT<4>.Q | D_OUT<7>.D | 9.000 |
D_OUT<5>.Q | D_OUT<6>.D | 9.000 |
D_OUT<5>.Q | D_OUT<7>.D | 9.000 |
D_OUT<6>.Q | D_OUT<7>.D | 9.000 |
D_OUT<0>.Q | D_OUT<0>.D | 8.000 |
D_OUT<0>.Q | D_OUT<1>.D | 8.000 |
D_OUT<1>.Q | D_OUT<1>.D | 8.000 |
D_OUT<2>.Q | D_OUT<2>.D | 8.000 |
D_OUT<2>.Q | D_OUT<6>.D | 8.000 |
D_OUT<3>.Q | D_OUT<3>.D | 8.000 |
D_OUT<4>.Q | D_OUT<4>.D | 8.000 |
D_OUT<5>.Q | D_OUT<5>.D | 8.000 |
D_OUT<6>.Q | D_OUT<6>.D | 8.000 |
D_OUT<7>.Q | D_OUT<7>.D | 8.000 |
Source Pad | Destination Pad | Delay |
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