cpldfit:  version J.33                              Xilinx Inc.
                                  Fitter Report
Design Name: vollad_rtl                          Date:  1-10-2010, 11:50AM
Device Used: XC95108-7-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
8  /108 (  7%) 65  /540  ( 12%) 26 /216 ( 12%)   0  /108 (  0%) 15 /69  ( 22%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           1/18        3/36        3           3/90       1/12
FB2           3/18        9/36        9          46/90       1/12
FB3           1/18        5/36        5           7/90       1/12
FB4           1/18        3/36        3           3/90       1/11
FB5           1/18        3/36        3           3/90       1/11
FB6           1/18        3/36        3           3/90       1/11
             -----       -----                   -----       -----     
              8/108      26/216                  65/540      6/69 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    9           9    |  I/O              :    15      63
Output        :    6           6    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     15          15

** Power Data **

There are 8 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 6 Outputs **

Signal                                                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                        Pts   Inps          No.  Type    Use     Mode Rate State
CO                                                          3     3     FB1_2   1    I/O     O       STD  FAST 
ZERO                                                        24    9     FB2_6   75   I/O     O       STD  FAST 
S<1>                                                        7     5     FB3_3   15   I/O     O       STD  FAST 
S<0>                                                        3     3     FB4_2   57   I/O     O       STD  FAST 
S<2>                                                        3     3     FB5_2   32   I/O     O       STD  FAST 
S<3>                                                        3     3     FB6_2   45   I/O     O       STD  FAST 

** 2 Buried Nodes **

Signal                                                      Total Total Loc     Pwr  Reg Init
Name                                                        Pts   Inps          Mode State
Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2  15    7     FB2_1   STD  
Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2  7     5     FB2_18  STD  

** 9 Inputs **

Signal                                                      Loc     Pin  Pin     Pin     
Name                                                                No.  Type    Use     
CI                                                          FB1_8   5    I/O     I
A<1>                                                        FB2_3   72   I/O     I
A<0>                                                        FB2_16  83   I/O     I
A<3>                                                        FB3_2   14   I/O     I
A<2>                                                        FB3_5   17   I/O     I
B<2>                                                        FB4_17  70   I/O     I
B<3>                                                        FB5_9   37   I/O     I
B<1>                                                        FB5_17  44   I/O     I
B<0>                                                        FB6_12  53   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               3/33
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
CO                    3       0     0   2     FB1_2   1     I/O     O
(unused)              0       0     0   5     FB1_3   2     I/O     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   3     I/O     
(unused)              0       0     0   5     FB1_6   4     I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   5     I/O     I
(unused)              0       0     0   5     FB1_9   6     I/O     
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  7     I/O     
(unused)              0       0     0   5     FB1_12  9     GCK/I/O 
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  10    GCK/I/O 
(unused)              0       0     0   5     FB1_15  11    I/O     
(unused)              0       0     0   5     FB1_16  12    GCK/I/O 
(unused)              0       0     0   5     FB1_17  13    I/O     
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: A<3>               2: B<3>               3: Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CO                   XXX..................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               9/27
Number of signals used by logic mapping into function block:  9
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2
                     15      10<-   0   0     FB2_1         (b)     (b)
(unused)              0       0   /\5   0     FB2_2   71    I/O     (b)
(unused)              0       0   /\1   4     FB2_3   72    I/O     I
(unused)              0       0   \/5   0     FB2_4         (b)     (b)
(unused)              0       0   \/5   0     FB2_5   74    GSR/I/O (b)
ZERO                 24      19<-   0   0     FB2_6   75    I/O     O
(unused)              0       0   /\5   0     FB2_7         (b)     (b)
(unused)              0       0   /\4   1     FB2_8   76    GTS/I/O (b)
(unused)              0       0     0   5     FB2_9   77    GTS/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  79    I/O     
(unused)              0       0     0   5     FB2_12  80    I/O     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  81    I/O     
(unused)              0       0     0   5     FB2_15  82    I/O     
(unused)              0       0   \/1   4     FB2_16  83    I/O     I
(unused)              0       0   \/5   0     FB2_17  84    I/O     (b)
Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2
                      7       6<- \/4   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: A<0>               4: A<3>               7: B<2> 
  2: A<1>               5: B<0>               8: B<3> 
  3: A<2>               6: B<1>               9: CI 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2 
                     XXX.XXX.X............................... 7       7
ZERO                 XXXXXXXXX............................... 9       9
Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2 
                     XX..XX..X............................... 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               5/31
Number of signals used by logic mapping into function block:  5
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0   \/1   4     FB3_2   14    I/O     I
S<1>                  7       2<-   0   0     FB3_3   15    I/O     O
(unused)              0       0   /\1   4     FB3_4         (b)     (b)
(unused)              0       0     0   5     FB3_5   17    I/O     I
(unused)              0       0     0   5     FB3_6   18    I/O     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   19    I/O     
(unused)              0       0     0   5     FB3_9   20    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  21    I/O     
(unused)              0       0     0   5     FB3_12  23    I/O     
(unused)              0       0     0   5     FB3_13        (b)     
(unused)              0       0     0   5     FB3_14  24    I/O     
(unused)              0       0     0   5     FB3_15  25    I/O     
(unused)              0       0     0   5     FB3_16  26    I/O     
(unused)              0       0     0   5     FB3_17  31    I/O     
(unused)              0       0     0   5     FB3_18        (b)     

Signals Used by Logic in Function Block
  1: A<0>               3: B<0>               5: CI 
  2: A<1>               4: B<1>             

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
S<1>                 XXXXX................................... 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               3/33
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
S<0>                  3       0     0   2     FB4_2   57    I/O     O
(unused)              0       0     0   5     FB4_3   58    I/O     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   61    I/O     
(unused)              0       0     0   5     FB4_6   62    I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   63    I/O     
(unused)              0       0     0   5     FB4_9   65    I/O     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  66    I/O     
(unused)              0       0     0   5     FB4_12  67    I/O     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  68    I/O     
(unused)              0       0     0   5     FB4_15  69    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  70    I/O     I
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block
  1: A<0>               2: B<0>               3: CI 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
S<0>                 XXX..................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               3/33
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
S<2>                  3       0     0   2     FB5_2   32    I/O     O
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     
(unused)              0       0     0   5     FB5_9   37    I/O     I
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     I
(unused)              0       0     0   5     FB5_18        (b)     

Signals Used by Logic in Function Block
  1: A<2>               2: B<2>               3: Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
S<2>                 XXX..................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               3/33
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
S<3>                  3       0     0   2     FB6_2   45    I/O     O
(unused)              0       0     0   5     FB6_3   46    I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   47    I/O     
(unused)              0       0     0   5     FB6_6   48    I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   50    I/O     
(unused)              0       0     0   5     FB6_9   51    I/O     
(unused)              0       0     0   5     FB6_10        (b)     
(unused)              0       0     0   5     FB6_11  52    I/O     
(unused)              0       0     0   5     FB6_12  53    I/O     I
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  54    I/O     
(unused)              0       0     0   5     FB6_15  55    I/O     
(unused)              0       0     0   5     FB6_16        (b)     
(unused)              0       0     0   5     FB6_17  56    I/O     
(unused)              0       0     0   5     FB6_18        (b)     

Signals Used by Logic in Function Block
  1: A<3>               2: B<3>               3: Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
S<3>                 XXX..................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


CO <= ((B(3) AND A(3))
	OR (B(3) AND 
	Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2)
	OR (A(3) AND 
	Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2));






















Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2 <= ((EXP7_.EXP)
	OR (A(1) AND B(1)));


Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2 <= ((EXP0_.EXP)
	OR (
	Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2.EXP)
	OR (A(1) AND B(1) AND A(2))
	OR (CI AND A(0) AND A(1) AND A(2))
	OR (CI AND B(0) AND A(1) AND A(2))
	OR (A(0) AND B(0) AND A(1) AND A(2))
	OR (A(0) AND B(0) AND B(1) AND A(2)));


S(0) <= NOT (A(0)
	 XOR 
S(0) <= NOT (((CI AND B(0))
	OR (NOT CI AND NOT B(0))));


S(1) <= NOT (A(1)
	 XOR 
S(1) <= NOT (((EXP8_.EXP)
	OR (EXP9_.EXP)
	OR (CI AND A(0) AND B(1))
	OR (NOT CI AND NOT A(0) AND NOT B(1))
	OR (A(0) AND B(0) AND B(1))
	OR (NOT A(0) AND NOT B(0) AND NOT B(1))));


S(2) <= NOT (A(2)
	 XOR 
S(2) <= NOT (((B(2) AND 
	Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2)
	OR (NOT B(2) AND 
	NOT Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2)));


S(3) <= NOT (A(3)
	 XOR 
S(3) <= NOT (((B(3) AND 
	Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2)
	OR (NOT B(3) AND 
	NOT Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2)));


ZERO <= NOT (((EXP3_.EXP)
	OR (EXP4_.EXP)
	OR (B(3) AND A(3) AND A(1))
	OR (NOT B(3) AND NOT A(3) AND A(1))
	OR (NOT CI AND NOT B(0) AND NOT A(1) AND B(1))
	OR (B(3) AND NOT A(3) AND NOT A(2) AND NOT B(2))
	OR (NOT B(3) AND A(3) AND NOT A(2) AND NOT B(2))));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-7-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
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 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-7-PC84                     65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
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 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 CO                               43 TIE                           
  2 TIE                              44 B<1>                          
  3 TIE                              45 S<3>                          
  4 TIE                              46 TIE                           
  5 CI                               47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 TIE                              51 TIE                           
 10 TIE                              52 TIE                           
 11 TIE                              53 B<0>                          
 12 TIE                              54 TIE                           
 13 TIE                              55 TIE                           
 14 A<3>                             56 TIE                           
 15 S<1>                             57 S<0>                          
 16 GND                              58 TIE                           
 17 A<2>                             59 TDO                           
 18 TIE                              60 GND                           
 19 TIE                              61 TIE                           
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 TIE                           
 24 TIE                              66 TIE                           
 25 TIE                              67 TIE                           
 26 TIE                              68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 B<2>                          
 29 TMS                              71 TIE                           
 30 TCK                              72 A<1>                          
 31 TIE                              73 VCC                           
 32 S<2>                             74 TIE                           
 33 TIE                              75 ZERO                          
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 B<3>                             79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 TIE                           
 40 TIE                              82 TIE                           
 41 TIE                              83 A<0>                          
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-7-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25