Timing Report

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Design Name addbit_rtl_1
Device, Speed (SpeedFile Version) XC95108, -7 (3.0)
Date Created Sun Jan 10 11:29:23 2010
Created By Timing Report Generator: version J.33
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Pad to Pad Delay (tPD) 7.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 7.5 6 6
AUTO_TS_P2F 0.0 0.0 0 0
AUTO_TS_F2P 0.0 0.0 0 0


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A to CO 0.000 7.500 -7.500
A to S 0.000 7.500 -7.500
B to CO 0.000 7.500 -7.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 1

Data Sheet Report

Pad to Pad List

Source Pad Destination Pad Delay
A CO 7.500
A S 7.500
B CO 7.500
B S 7.500
CI CO 7.500
CI S 7.500



Number of paths analyzed: 6
Number of Timing errors: 6
Analysis Completed: Sun Jan 10 11:29:23 2010