cpldfit:  version J.33                              Xilinx Inc.
                                  Fitter Report
Design Name: simple_ctr_1                        Date:  1-17-2010, 12:50PM
Device Used: XC95108-7-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
24 /108 ( 22%) 23  /540  (  4%) 121/216 ( 56%)   24 /108 ( 22%) 9  /69  ( 13%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           2/18       17/36       17           2/90       2/12
FB2           2/18       21/36       21           2/90       2/12
FB3          16/18       23/36       23          16/90       1/12
FB4           2/18       22/36       22           1/90       1/11
FB5           1/18       18/36       18           1/90       1/11
FB6           1/18       20/36       20           1/90       1/11
             -----       -----                   -----       -----     
             24/108     121/216                  23/540      8/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'C' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :     8      63
Output        :    8           8    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      9           9

** Power Data **

There are 24 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 8 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
LED<16>             1     16    FB1_2   1    I/O     O       STD  SLOW RESET
LED<17>             1     17    FB1_9   6    I/O     O       STD  SLOW RESET
LED<19>             1     19    FB2_2   71   I/O     O       STD  SLOW RESET
LED<21>             1     21    FB2_14  81   I/O     O       STD  SLOW RESET
LED<23>             1     23    FB3_2   14   I/O     O       STD  SLOW RESET
LED<22>             1     22    FB4_2   57   I/O     O       STD  SLOW RESET
LED<18>             1     18    FB5_2   32   I/O     O       STD  SLOW RESET
LED<20>             1     20    FB6_2   45   I/O     O       STD  SLOW RESET

** 16 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
ctr/CNT_L<9>        1     9     FB3_4   STD  RESET
ctr/CNT_L<8>        1     8     FB3_5   STD  RESET
ctr/CNT_L<7>        1     7     FB3_6   STD  RESET
ctr/CNT_L<6>        1     6     FB3_7   STD  RESET
ctr/CNT_L<5>        1     5     FB3_8   STD  RESET
ctr/CNT_L<4>        1     4     FB3_9   STD  RESET
ctr/CNT_L<3>        1     3     FB3_10  STD  RESET
ctr/CNT_L<2>        1     2     FB3_11  STD  RESET
ctr/CNT_L<1>        1     1     FB3_12  STD  RESET
ctr/CNT_L<15>       1     15    FB3_13  STD  RESET
ctr/CNT_L<14>       1     14    FB3_14  STD  RESET
ctr/CNT_L<13>       1     13    FB3_15  STD  RESET
ctr/CNT_L<12>       1     12    FB3_16  STD  RESET
ctr/CNT_L<11>       1     11    FB3_17  STD  RESET
ctr/CNT_L<10>       1     10    FB3_18  STD  RESET
ctr/CNT_L<0>        0     0     FB4_18  STD  RESET

** 1 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
C                   FB1_12  9~   GCK/I/O GCK

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               17/19
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
LED<16>               1       0     0   4     FB1_2   1     I/O     O
(unused)              0       0     0   5     FB1_3   2     I/O     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   3     I/O     
(unused)              0       0     0   5     FB1_6   4     I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   5     I/O     
LED<17>               1       0     0   4     FB1_9   6     I/O     O
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  7     I/O     
(unused)              0       0     0   5     FB1_12  9     GCK/I/O GCK
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  10    GCK/I/O 
(unused)              0       0     0   5     FB1_15  11    I/O     
(unused)              0       0     0   5     FB1_16  12    GCK/I/O 
(unused)              0       0     0   5     FB1_17  13    I/O     
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: LED_16_OBUF.LFBK   7: ctr/CNT_L<14>     13: ctr/CNT_L<5> 
  2: ctr/CNT_L<0>       8: ctr/CNT_L<15>     14: ctr/CNT_L<6> 
  3: ctr/CNT_L<10>      9: ctr/CNT_L<1>      15: ctr/CNT_L<7> 
  4: ctr/CNT_L<11>     10: ctr/CNT_L<2>      16: ctr/CNT_L<8> 
  5: ctr/CNT_L<12>     11: ctr/CNT_L<3>      17: ctr/CNT_L<9> 
  6: ctr/CNT_L<13>     12: ctr/CNT_L<4>     

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED<16>              .XXXXXXXXXXXXXXXX....................... 16      16
LED<17>              XXXXXXXXXXXXXXXXX....................... 17      17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               21/15
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
LED<19>               1       0     0   4     FB2_2   71    I/O     O
(unused)              0       0     0   5     FB2_3   72    I/O     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   74    GSR/I/O 
(unused)              0       0     0   5     FB2_6   75    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   76    GTS/I/O 
(unused)              0       0     0   5     FB2_9   77    GTS/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  79    I/O     
(unused)              0       0     0   5     FB2_12  80    I/O     
(unused)              0       0     0   5     FB2_13        (b)     
LED<21>               1       0     0   4     FB2_14  81    I/O     O
(unused)              0       0     0   5     FB2_15  82    I/O     
(unused)              0       0     0   5     FB2_16  83    I/O     
(unused)              0       0     0   5     FB2_17  84    I/O     
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: LED<16>            8: ctr/CNT_L<11>     15: ctr/CNT_L<3> 
  2: LED<17>            9: ctr/CNT_L<12>     16: ctr/CNT_L<4> 
  3: LED<18>           10: ctr/CNT_L<13>     17: ctr/CNT_L<5> 
  4: LED<20>           11: ctr/CNT_L<14>     18: ctr/CNT_L<6> 
  5: LED_19_OBUF.LFBK  12: ctr/CNT_L<15>     19: ctr/CNT_L<7> 
  6: ctr/CNT_L<0>      13: ctr/CNT_L<1>      20: ctr/CNT_L<8> 
  7: ctr/CNT_L<10>     14: ctr/CNT_L<2>      21: ctr/CNT_L<9> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED<19>              XXX..XXXXXXXXXXXXXXXX................... 19      19
LED<21>              XXXXXXXXXXXXXXXXXXXXX................... 21      21
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               23/13
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
LED<23>               1       0     0   4     FB3_2   14    I/O     O
(unused)              0       0     0   5     FB3_3   15    I/O     
ctr/CNT_L<9>          1       0     0   4     FB3_4         (b)     (b)
ctr/CNT_L<8>          1       0     0   4     FB3_5   17    I/O     (b)
ctr/CNT_L<7>          1       0     0   4     FB3_6   18    I/O     (b)
ctr/CNT_L<6>          1       0     0   4     FB3_7         (b)     (b)
ctr/CNT_L<5>          1       0     0   4     FB3_8   19    I/O     (b)
ctr/CNT_L<4>          1       0     0   4     FB3_9   20    I/O     (b)
ctr/CNT_L<3>          1       0     0   4     FB3_10        (b)     (b)
ctr/CNT_L<2>          1       0     0   4     FB3_11  21    I/O     (b)
ctr/CNT_L<1>          1       0     0   4     FB3_12  23    I/O     (b)
ctr/CNT_L<15>         1       0     0   4     FB3_13        (b)     (b)
ctr/CNT_L<14>         1       0     0   4     FB3_14  24    I/O     (b)
ctr/CNT_L<13>         1       0     0   4     FB3_15  25    I/O     (b)
ctr/CNT_L<12>         1       0     0   4     FB3_16  26    I/O     (b)
ctr/CNT_L<11>         1       0     0   4     FB3_17  31    I/O     (b)
ctr/CNT_L<10>         1       0     0   4     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: LED<16>            9: ctr/CNT_L<10>.LFBK  17: ctr/CNT_L<3>.LFBK 
  2: LED<17>           10: ctr/CNT_L<11>.LFBK  18: ctr/CNT_L<4>.LFBK 
  3: LED<18>           11: ctr/CNT_L<12>.LFBK  19: ctr/CNT_L<5>.LFBK 
  4: LED<19>           12: ctr/CNT_L<13>.LFBK  20: ctr/CNT_L<6>.LFBK 
  5: LED<20>           13: ctr/CNT_L<14>.LFBK  21: ctr/CNT_L<7>.LFBK 
  6: LED<21>           14: ctr/CNT_L<15>.LFBK  22: ctr/CNT_L<8>.LFBK 
  7: LED<22>           15: ctr/CNT_L<1>.LFBK   23: ctr/CNT_L<9>.LFBK 
  8: ctr/CNT_L<0>      16: ctr/CNT_L<2>.LFBK  

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED<23>              XXXXXXXXXXXXXXXXXXXXXXX................. 23      23
ctr/CNT_L<9>         .......X......XXXXXXXX.................. 9       9
ctr/CNT_L<8>         .......X......XXXXXXX................... 8       8
ctr/CNT_L<7>         .......X......XXXXXX.................... 7       7
ctr/CNT_L<6>         .......X......XXXXX..................... 6       6
ctr/CNT_L<5>         .......X......XXXX...................... 5       5
ctr/CNT_L<4>         .......X......XXX....................... 4       4
ctr/CNT_L<3>         .......X......XX........................ 3       3
ctr/CNT_L<2>         .......X......X......................... 2       2
ctr/CNT_L<1>         .......X................................ 1       1
ctr/CNT_L<15>        .......XXXXXX.XXXXXXXXX................. 15      15
ctr/CNT_L<14>        .......XXXXX..XXXXXXXXX................. 14      14
ctr/CNT_L<13>        .......XXXX...XXXXXXXXX................. 13      13
ctr/CNT_L<12>        .......XXX....XXXXXXXXX................. 12      12
ctr/CNT_L<11>        .......XX.....XXXXXXXXX................. 11      11
ctr/CNT_L<10>        .......X......XXXXXXXXX................. 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               22/14
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
LED<22>               1       0     0   4     FB4_2   57    I/O     O
(unused)              0       0     0   5     FB4_3   58    I/O     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   61    I/O     
(unused)              0       0     0   5     FB4_6   62    I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   63    I/O     
(unused)              0       0     0   5     FB4_9   65    I/O     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  66    I/O     
(unused)              0       0     0   5     FB4_12  67    I/O     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  68    I/O     
(unused)              0       0     0   5     FB4_15  69    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  70    I/O     
ctr/CNT_L<0>          0       0     0   5     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: LED<16>             9: ctr/CNT_L<11>     16: ctr/CNT_L<3> 
  2: LED<17>            10: ctr/CNT_L<12>     17: ctr/CNT_L<4> 
  3: LED<18>            11: ctr/CNT_L<13>     18: ctr/CNT_L<5> 
  4: LED<19>            12: ctr/CNT_L<14>     19: ctr/CNT_L<6> 
  5: LED<20>            13: ctr/CNT_L<15>     20: ctr/CNT_L<7> 
  6: LED<21>            14: ctr/CNT_L<1>      21: ctr/CNT_L<8> 
  7: ctr/CNT_L<0>.LFBK  15: ctr/CNT_L<2>      22: ctr/CNT_L<9> 
  8: ctr/CNT_L<10>     

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED<22>              XXXXXXXXXXXXXXXXXXXXXX.................. 22      22
ctr/CNT_L<0>         ........................................ 0       0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
LED<18>               1       0     0   4     FB5_2   32    I/O     O
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     
(unused)              0       0     0   5     FB5_9   37    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     

Signals Used by Logic in Function Block
  1: LED<16>            7: ctr/CNT_L<13>     13: ctr/CNT_L<4> 
  2: LED<17>            8: ctr/CNT_L<14>     14: ctr/CNT_L<5> 
  3: ctr/CNT_L<0>       9: ctr/CNT_L<15>     15: ctr/CNT_L<6> 
  4: ctr/CNT_L<10>     10: ctr/CNT_L<1>      16: ctr/CNT_L<7> 
  5: ctr/CNT_L<11>     11: ctr/CNT_L<2>      17: ctr/CNT_L<8> 
  6: ctr/CNT_L<12>     12: ctr/CNT_L<3>      18: ctr/CNT_L<9> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED<18>              XXXXXXXXXXXXXXXXXX...................... 18      18
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               20/16
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
LED<20>               1       0     0   4     FB6_2   45    I/O     O
(unused)              0       0     0   5     FB6_3   46    I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   47    I/O     
(unused)              0       0     0   5     FB6_6   48    I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   50    I/O     
(unused)              0       0     0   5     FB6_9   51    I/O     
(unused)              0       0     0   5     FB6_10        (b)     
(unused)              0       0     0   5     FB6_11  52    I/O     
(unused)              0       0     0   5     FB6_12  53    I/O     
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  54    I/O     
(unused)              0       0     0   5     FB6_15  55    I/O     
(unused)              0       0     0   5     FB6_16        (b)     
(unused)              0       0     0   5     FB6_17  56    I/O     
(unused)              0       0     0   5     FB6_18        (b)     

Signals Used by Logic in Function Block
  1: LED<16>            8: ctr/CNT_L<12>     15: ctr/CNT_L<4> 
  2: LED<17>            9: ctr/CNT_L<13>     16: ctr/CNT_L<5> 
  3: LED<18>           10: ctr/CNT_L<14>     17: ctr/CNT_L<6> 
  4: LED<19>           11: ctr/CNT_L<15>     18: ctr/CNT_L<7> 
  5: ctr/CNT_L<0>      12: ctr/CNT_L<1>      19: ctr/CNT_L<8> 
  6: ctr/CNT_L<10>     13: ctr/CNT_L<2>      20: ctr/CNT_L<9> 
  7: ctr/CNT_L<11>     14: ctr/CNT_L<3>     

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED<20>              XXXXXXXXXXXXXXXXXXXX.................... 20      20
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_LED16: FTCPE port map (LED(16),LED_T(16),C,'0','0');
LED_T(16) <= (ctr/CNT_L(0) AND ctr/CNT_L(10) AND ctr/CNT_L(11) AND 
	ctr/CNT_L(12) AND ctr/CNT_L(13) AND ctr/CNT_L(14) AND ctr/CNT_L(1) AND 
	ctr/CNT_L(2) AND ctr/CNT_L(3) AND ctr/CNT_L(4) AND ctr/CNT_L(5) AND 
	ctr/CNT_L(6) AND ctr/CNT_L(7) AND ctr/CNT_L(8) AND ctr/CNT_L(9) AND 
	ctr/CNT_L(15));

FTCPE_LED17: FTCPE port map (LED(17),LED_T(17),C,'0','0');
LED_T(17) <= (ctr/CNT_L(0) AND ctr/CNT_L(10) AND ctr/CNT_L(11) AND 
	ctr/CNT_L(12) AND ctr/CNT_L(13) AND ctr/CNT_L(14) AND ctr/CNT_L(1) AND 
	ctr/CNT_L(2) AND ctr/CNT_L(3) AND ctr/CNT_L(4) AND ctr/CNT_L(5) AND 
	ctr/CNT_L(6) AND ctr/CNT_L(7) AND ctr/CNT_L(8) AND ctr/CNT_L(9) AND 
	ctr/CNT_L(15) AND LED_16_OBUF.LFBK);

FTCPE_LED18: FTCPE port map (LED(18),LED_T(18),C,'0','0');
LED_T(18) <= (LED(16) AND LED(17) AND ctr/CNT_L(0) AND 
	ctr/CNT_L(10) AND ctr/CNT_L(11) AND ctr/CNT_L(12) AND ctr/CNT_L(13) AND 
	ctr/CNT_L(14) AND ctr/CNT_L(1) AND ctr/CNT_L(2) AND ctr/CNT_L(3) AND 
	ctr/CNT_L(4) AND ctr/CNT_L(5) AND ctr/CNT_L(6) AND ctr/CNT_L(7) AND 
	ctr/CNT_L(8) AND ctr/CNT_L(9) AND ctr/CNT_L(15));

FTCPE_LED19: FTCPE port map (LED(19),LED_T(19),C,'0','0');
LED_T(19) <= (LED(16) AND LED(17) AND LED(18) AND ctr/CNT_L(0) AND 
	ctr/CNT_L(10) AND ctr/CNT_L(11) AND ctr/CNT_L(12) AND ctr/CNT_L(13) AND 
	ctr/CNT_L(14) AND ctr/CNT_L(1) AND ctr/CNT_L(2) AND ctr/CNT_L(3) AND 
	ctr/CNT_L(4) AND ctr/CNT_L(5) AND ctr/CNT_L(6) AND ctr/CNT_L(7) AND 
	ctr/CNT_L(8) AND ctr/CNT_L(9) AND ctr/CNT_L(15));

FTCPE_LED20: FTCPE port map (LED(20),LED_T(20),C,'0','0');
LED_T(20) <= (LED(16) AND LED(17) AND LED(18) AND LED(19) AND 
	ctr/CNT_L(0) AND ctr/CNT_L(10) AND ctr/CNT_L(11) AND ctr/CNT_L(12) AND 
	ctr/CNT_L(13) AND ctr/CNT_L(14) AND ctr/CNT_L(1) AND ctr/CNT_L(2) AND 
	ctr/CNT_L(3) AND ctr/CNT_L(4) AND ctr/CNT_L(5) AND ctr/CNT_L(6) AND 
	ctr/CNT_L(7) AND ctr/CNT_L(8) AND ctr/CNT_L(9) AND ctr/CNT_L(15));

FTCPE_LED21: FTCPE port map (LED(21),LED_T(21),C,'0','0');
LED_T(21) <= (LED(16) AND LED(17) AND LED(18) AND LED(20) AND 
	ctr/CNT_L(0) AND ctr/CNT_L(10) AND ctr/CNT_L(11) AND ctr/CNT_L(12) AND 
	ctr/CNT_L(13) AND ctr/CNT_L(14) AND ctr/CNT_L(1) AND ctr/CNT_L(2) AND 
	ctr/CNT_L(3) AND ctr/CNT_L(4) AND ctr/CNT_L(5) AND ctr/CNT_L(6) AND 
	ctr/CNT_L(7) AND ctr/CNT_L(8) AND ctr/CNT_L(9) AND ctr/CNT_L(15) AND 
	LED_19_OBUF.LFBK);

FTCPE_LED22: FTCPE port map (LED(22),LED_T(22),C,'0','0');
LED_T(22) <= (LED(16) AND LED(17) AND LED(18) AND LED(19) AND 
	LED(20) AND LED(21) AND ctr/CNT_L(10) AND ctr/CNT_L(11) AND 
	ctr/CNT_L(12) AND ctr/CNT_L(13) AND ctr/CNT_L(14) AND ctr/CNT_L(1) AND 
	ctr/CNT_L(2) AND ctr/CNT_L(3) AND ctr/CNT_L(4) AND ctr/CNT_L(5) AND 
	ctr/CNT_L(6) AND ctr/CNT_L(7) AND ctr/CNT_L(8) AND ctr/CNT_L(9) AND 
	ctr/CNT_L(15) AND ctr/CNT_L(0).LFBK);

FTCPE_LED23: FTCPE port map (LED(23),LED_T(23),C,'0','0');
LED_T(23) <= (LED(16) AND LED(17) AND LED(18) AND LED(19) AND 
	LED(20) AND LED(21) AND LED(22) AND ctr/CNT_L(0) AND 
	ctr/CNT_L(10).LFBK AND ctr/CNT_L(11).LFBK AND ctr/CNT_L(12).LFBK AND 
	ctr/CNT_L(13).LFBK AND ctr/CNT_L(14).LFBK AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK AND 
	ctr/CNT_L(8).LFBK AND ctr/CNT_L(9).LFBK AND ctr/CNT_L(15).LFBK);

FTCPE_ctr/CNT_L0: FTCPE port map (ctr/CNT_L(0),'1',C,'0','0');

FTCPE_ctr/CNT_L1: FTCPE port map (ctr/CNT_L(1),ctr/CNT_L(0),C,'0','0');

FTCPE_ctr/CNT_L2: FTCPE port map (ctr/CNT_L(2),ctr/CNT_L_T(2),C,'0','0');
ctr/CNT_L_T(2) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK);

FTCPE_ctr/CNT_L3: FTCPE port map (ctr/CNT_L(3),ctr/CNT_L_T(3),C,'0','0');
ctr/CNT_L_T(3) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK);

FTCPE_ctr/CNT_L4: FTCPE port map (ctr/CNT_L(4),ctr/CNT_L_T(4),C,'0','0');
ctr/CNT_L_T(4) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK);

FTCPE_ctr/CNT_L5: FTCPE port map (ctr/CNT_L(5),ctr/CNT_L_T(5),C,'0','0');
ctr/CNT_L_T(5) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK);

FTCPE_ctr/CNT_L6: FTCPE port map (ctr/CNT_L(6),ctr/CNT_L_T(6),C,'0','0');
ctr/CNT_L_T(6) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK);

FTCPE_ctr/CNT_L7: FTCPE port map (ctr/CNT_L(7),ctr/CNT_L_T(7),C,'0','0');
ctr/CNT_L_T(7) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK);

FTCPE_ctr/CNT_L8: FTCPE port map (ctr/CNT_L(8),ctr/CNT_L_T(8),C,'0','0');
ctr/CNT_L_T(8) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK);

FTCPE_ctr/CNT_L9: FTCPE port map (ctr/CNT_L(9),ctr/CNT_L_T(9),C,'0','0');
ctr/CNT_L_T(9) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK AND 
	ctr/CNT_L(8).LFBK);

FTCPE_ctr/CNT_L10: FTCPE port map (ctr/CNT_L(10),ctr/CNT_L_T(10),C,'0','0');
ctr/CNT_L_T(10) <= (ctr/CNT_L(0) AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK AND 
	ctr/CNT_L(8).LFBK AND ctr/CNT_L(9).LFBK);

FTCPE_ctr/CNT_L11: FTCPE port map (ctr/CNT_L(11),ctr/CNT_L_T(11),C,'0','0');
ctr/CNT_L_T(11) <= (ctr/CNT_L(0) AND ctr/CNT_L(10).LFBK AND 
	ctr/CNT_L(1).LFBK AND ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND 
	ctr/CNT_L(4).LFBK AND ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND 
	ctr/CNT_L(7).LFBK AND ctr/CNT_L(8).LFBK AND ctr/CNT_L(9).LFBK);

FTCPE_ctr/CNT_L12: FTCPE port map (ctr/CNT_L(12),ctr/CNT_L_T(12),C,'0','0');
ctr/CNT_L_T(12) <= (ctr/CNT_L(0) AND ctr/CNT_L(10).LFBK AND 
	ctr/CNT_L(11).LFBK AND ctr/CNT_L(1).LFBK AND ctr/CNT_L(2).LFBK AND 
	ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND ctr/CNT_L(5).LFBK AND 
	ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK AND ctr/CNT_L(8).LFBK AND 
	ctr/CNT_L(9).LFBK);

FTCPE_ctr/CNT_L13: FTCPE port map (ctr/CNT_L(13),ctr/CNT_L_T(13),C,'0','0');
ctr/CNT_L_T(13) <= (ctr/CNT_L(0) AND ctr/CNT_L(10).LFBK AND 
	ctr/CNT_L(11).LFBK AND ctr/CNT_L(12).LFBK AND ctr/CNT_L(1).LFBK AND 
	ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND 
	ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK AND 
	ctr/CNT_L(8).LFBK AND ctr/CNT_L(9).LFBK);

FTCPE_ctr/CNT_L14: FTCPE port map (ctr/CNT_L(14),ctr/CNT_L_T(14),C,'0','0');
ctr/CNT_L_T(14) <= (ctr/CNT_L(0) AND ctr/CNT_L(10).LFBK AND 
	ctr/CNT_L(11).LFBK AND ctr/CNT_L(12).LFBK AND ctr/CNT_L(13).LFBK AND 
	ctr/CNT_L(1).LFBK AND ctr/CNT_L(2).LFBK AND ctr/CNT_L(3).LFBK AND 
	ctr/CNT_L(4).LFBK AND ctr/CNT_L(5).LFBK AND ctr/CNT_L(6).LFBK AND 
	ctr/CNT_L(7).LFBK AND ctr/CNT_L(8).LFBK AND ctr/CNT_L(9).LFBK);

FTCPE_ctr/CNT_L15: FTCPE port map (ctr/CNT_L(15),ctr/CNT_L_T(15),C,'0','0');
ctr/CNT_L_T(15) <= (ctr/CNT_L(0) AND ctr/CNT_L(10).LFBK AND 
	ctr/CNT_L(11).LFBK AND ctr/CNT_L(12).LFBK AND ctr/CNT_L(13).LFBK AND 
	ctr/CNT_L(14).LFBK AND ctr/CNT_L(1).LFBK AND ctr/CNT_L(2).LFBK AND 
	ctr/CNT_L(3).LFBK AND ctr/CNT_L(4).LFBK AND ctr/CNT_L(5).LFBK AND 
	ctr/CNT_L(6).LFBK AND ctr/CNT_L(7).LFBK AND ctr/CNT_L(8).LFBK AND 
	ctr/CNT_L(9).LFBK);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-7-PC84


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 | 21                       XC95108-7-PC84                     65 | 
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   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LED<16>                          43 PGND                          
  2 PGND                             44 PGND                          
  3 PGND                             45 LED<20>                       
  4 PGND                             46 PGND                          
  5 PGND                             47 PGND                          
  6 LED<17>                          48 PGND                          
  7 PGND                             49 GND                           
  8 GND                              50 PGND                          
  9 C                                51 PGND                          
 10 PGND                             52 PGND                          
 11 PGND                             53 PGND                          
 12 PGND                             54 PGND                          
 13 PGND                             55 PGND                          
 14 LED<23>                          56 PGND                          
 15 PGND                             57 LED<22>                       
 16 GND                              58 PGND                          
 17 PGND                             59 TDO                           
 18 PGND                             60 GND                           
 19 PGND                             61 PGND                          
 20 PGND                             62 PGND                          
 21 PGND                             63 PGND                          
 22 VCC                              64 VCC                           
 23 PGND                             65 PGND                          
 24 PGND                             66 PGND                          
 25 PGND                             67 PGND                          
 26 PGND                             68 PGND                          
 27 GND                              69 PGND                          
 28 TDI                              70 PGND                          
 29 TMS                              71 LED<19>                       
 30 TCK                              72 PGND                          
 31 PGND                             73 VCC                           
 32 LED<18>                          74 PGND                          
 33 PGND                             75 PGND                          
 34 PGND                             76 PGND                          
 35 PGND                             77 PGND                          
 36 PGND                             78 VCC                           
 37 PGND                             79 PGND                          
 38 VCC                              80 PGND                          
 39 PGND                             81 LED<21>                       
 40 PGND                             82 PGND                          
 41 PGND                             83 PGND                          
 42 GND                              84 PGND                          


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-7-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Ground on Unused IOs                        : ON
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25