Design Name | addbit_rtl_2 |
Device, Speed (SpeedFile Version) | XC95108, -7 (3.0) |
Date Created | Sun Jan 10 11:33:12 2010 |
Created By | Timing Report Generator: version J.33 |
Copyright | Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Pad to Pad Delay (tPD) | 7.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2P | 0.0 | 7.5 | 6 | 6 |
AUTO_TS_P2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2P | 0.0 | 0.0 | 0 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
A to CO | 0.000 | 7.500 | -7.500 |
A to S | 0.000 | 7.500 | -7.500 |
B to CO | 0.000 | 7.500 | -7.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Source Pad | Destination Pad | Delay |
---|---|---|
A | CO | 7.500 |
A | S | 7.500 |
B | CO | 7.500 |
B | S | 7.500 |
CI | CO | 7.500 |
CI | S | 7.500 |