Equations

********** Mapped Logic **********
FDCPE_D_OUT0: FDCPE port map (D_OUT(0),D_OUT_D(0),C,'0','0');
     D_OUT_D(0) <= ((LD AND NOT CLR AND D_IN(0))
      OR (CTF AND NOT LD AND NOT CLR AND NOT D_OUT_0.LFBK)
      OR (NOT LD AND NOT CLR AND CTB AND NOT D_OUT_0.LFBK)
      OR (NOT CTF AND NOT LD AND NOT CLR AND NOT CTB AND D_OUT_0.LFBK));
FTCPE_D_OUT1: FTCPE port map (D_OUT(1),D_OUT_T(1),C,'0','0');
     D_OUT_T(1) <= ((CLR AND D_OUT_1.LFBK)
      OR (LD AND NOT D_IN(1) AND D_OUT_1.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT_0.LFBK)
      OR (LD AND NOT CLR AND D_IN(1) AND NOT D_OUT_1.LFBK)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT_0.LFBK));
FTCPE_D_OUT2: FTCPE port map (D_OUT(2),D_OUT_T(2),C,'0','0');
     D_OUT_T(2) <= ((CLR AND D_OUT_2.LFBK)
      OR (LD AND NOT D_IN(2) AND D_OUT_2.LFBK)
      OR (LD AND NOT CLR AND D_IN(2) AND NOT D_OUT_2.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND
      NOT D_OUT(1).PIN));
FTCPE_D_OUT3: FTCPE port map (D_OUT(3),D_OUT_T(3),C,'0','0');
     D_OUT_T(3) <= ((CLR AND D_OUT_3.LFBK)
      OR (LD AND NOT D_IN(3) AND D_OUT_3.LFBK)
      OR (LD AND NOT CLR AND D_IN(3) AND NOT D_OUT_3.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND
      D_OUT(2).PIN)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND
      NOT D_OUT(1).PIN AND NOT D_OUT(2).PIN));
FTCPE_D_OUT4: FTCPE port map (D_OUT(4),D_OUT_T(4),C,'0','0');
     D_OUT_T(4) <= ((CLR AND D_OUT_4.LFBK)
      OR (LD AND NOT D_IN(4) AND D_OUT_4.LFBK)
      OR (LD AND NOT CLR AND D_IN(4) AND NOT D_OUT_4.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND
      D_OUT(2).PIN AND D_OUT(3).PIN)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND
      NOT D_OUT(1).PIN AND NOT D_OUT(2).PIN AND NOT D_OUT(3).PIN));
FTCPE_D_OUT5: FTCPE port map (D_OUT(5),D_OUT_T(5),C,'0','0');
     D_OUT_T(5) <= ((CLR AND D_OUT_5.LFBK)
      OR (LD AND NOT D_IN(5) AND D_OUT_5.LFBK)
      OR (LD AND NOT CLR AND D_IN(5) AND NOT D_OUT_5.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND
      D_OUT(2).PIN AND D_OUT(3).PIN AND D_OUT(4).PIN)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND
      NOT D_OUT(1).PIN AND NOT D_OUT(2).PIN AND NOT D_OUT(3).PIN AND NOT D_OUT(4).PIN));
FTCPE_D_OUT6: FTCPE port map (D_OUT(6),D_OUT_T(6),C,'0','0');
     D_OUT_T(6) <= ((CLR AND D_OUT_6.LFBK)
      OR (LD AND NOT D_IN(6) AND D_OUT_6.LFBK)
      OR (LD AND NOT CLR AND D_IN(6) AND NOT D_OUT_6.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT_2.LFBK AND D_OUT(0).PIN AND
      D_OUT(1).PIN AND D_OUT(3).PIN AND D_OUT(4).PIN AND D_OUT(5).PIN)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT_2.LFBK AND
      NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN AND NOT D_OUT(3).PIN AND NOT D_OUT(4).PIN AND
      NOT D_OUT(5).PIN));
FTCPE_D_OUT7: FTCPE port map (D_OUT(7),D_OUT_T(7),C,'0','0');
     D_OUT_T(7) <= ((CLR AND D_OUT_7.LFBK)
      OR (LD AND NOT D_IN(7) AND D_OUT_7.LFBK)
      OR (LD AND NOT CLR AND D_IN(7) AND NOT D_OUT_7.LFBK)
      OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND
      D_OUT(6).PIN AND D_OUT(2).PIN AND D_OUT(3).PIN AND D_OUT(4).PIN AND
      D_OUT(5).PIN)
      OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND
      NOT D_OUT(1).PIN AND NOT D_OUT(6).PIN AND NOT D_OUT(2).PIN AND NOT D_OUT(3).PIN AND
      NOT D_OUT(4).PIN AND NOT D_OUT(5).PIN));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);