cpldfit: version P.49d Xilinx Inc. Fitter Report Design Name: Zufall_01 Date: 7-18-2015, 11:16AM Device Used: XC9572-7-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 49 /72 ( 68%) 206 /360 ( 57%) 106/144 ( 74%) 40 /72 ( 56%) 26 /34 ( 76%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 8/18 16/36 16 29/90 2/ 9 FB2 13/18 30/36 30 58/90 5/ 9 FB3 16/18 30/36 30 63/90 6/ 8 FB4 12/18 30/36 30 56/90 4/ 8 ----- ----- ----- ----- 49/72 106/144 206/360 17/34 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. The complement of 'GTS_IN' mapped onto global output enable net GTS1. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 8 8 | I/O : 25 28 Output : 12 12 | GCK/IO : 0 3 Bidirectional : 5 5 | GTS/IO : 1 2 GCK : 0 0 | GSR/IO : 0 1 GTS : 1 1 | GSR : 0 0 | ---- ---- Total 26 26 ** Power Data ** There are 49 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'Zufall_01.ise'. WARNING:Cpld:908 - Converting I/O pin 'XBUS<5>' to an output pin. The pin feedback is unused after optimization. Please verify functionality via simulation. WARNING:Cpld:908 - Converting I/O pin 'XBUS<6>' to an output pin. The pin feedback is unused after optimization. Please verify functionality via simulation. WARNING:Cpld:908 - Converting I/O pin 'XBUS<7>' to an output pin. The pin feedback is unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 17 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State CT3A 2 6 FB1_15 8 I/O O STD SLOW SET CT3B 3 7 FB1_17 9 I/O O STD SLOW SET XBUS<3> 5 8 FB2_2 35 I/O I/O STD SLOW XBUS<2> 5 8 FB2_5 36 I/O I/O STD SLOW XBUS<1> 5 8 FB2_6 37 I/O I/O STD SLOW XBUS<0> 5 8 FB2_8 38 I/O I/O STD SLOW GTS_OUT 2 4 FB2_15 43 I/O O STD SLOW CT0A 2 6 FB3_2 11 I/O O STD SLOW SET CT0B 3 7 FB3_5 12 I/O O STD SLOW SET CT1A 2 6 FB3_8 13 I/O O STD SLOW SET CT1B 3 7 FB3_9 14 I/O O STD SLOW SET CT2A 2 6 FB3_11 18 I/O O STD SLOW SET CT2B 3 7 FB3_14 19 I/O O STD SLOW SET XBUS<7> 5 8 FB4_11 28 I/O O STD SLOW XBUS<6> 5 8 FB4_14 29 I/O O STD SLOW XBUS<5> 5 8 FB4_15 33 I/O O STD SLOW XBUS<4> 5 8 FB4_17 34 I/O I/O STD SLOW ** 32 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State CT3<7> 3 14 FB1_11 STD RESET CT3<0> 3 14 FB1_12 STD RESET CT3<6> 4 14 FB1_13 STD RESET CT3<1> 4 14 FB1_14 STD RESET CT3<5> 5 14 FB1_16 STD RESET CT3<2> 5 14 FB1_18 STD RESET CT0<7> 3 14 FB2_10 STD RESET CT0<0> 3 14 FB2_11 STD RESET CT0<6> 4 14 FB2_12 STD RESET CT0<1> 4 14 FB2_13 STD RESET CT0<5> 5 14 FB2_14 STD RESET CT0<2> 5 14 FB2_16 STD RESET CT0<4> 6 14 FB2_17 STD RESET CT0<3> 6 14 FB2_18 STD RESET CT2<7> 3 14 FB3_1 STD RESET CT2<0> 3 14 FB3_6 STD RESET CT2<6> 4 14 FB3_7 STD RESET CT2<1> 4 14 FB3_10 STD RESET CT2<5> 5 14 FB3_12 STD RESET CT2<2> 5 14 FB3_13 STD RESET CT3<4> 6 14 FB3_15 STD RESET CT3<3> 6 14 FB3_16 STD RESET CT2<4> 6 14 FB3_17 STD RESET CT2<3> 6 14 FB3_18 STD RESET CT1<7> 3 14 FB4_7 STD RESET CT1<0> 3 14 FB4_8 STD RESET CT1<6> 4 14 FB4_9 STD RESET CT1<1> 4 14 FB4_10 STD RESET CT1<5> 5 14 FB4_12 STD RESET CT1<2> 5 14 FB4_13 STD RESET CT1<4> 6 14 FB4_16 STD RESET CT1<3> 6 14 FB4_18 STD RESET ** 9 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use ENABLE FB1_2 1 I/O I SEL_2 FB1_5 2 I/O I SEL_1 FB1_6 3 I/O I SEL_0 FB1_8 4 I/O I GTS_IN FB2_14 42 GTS/I/O GTS COMP3 FB4_2 24 I/O I COMP2 FB4_5 25 I/O I COMP1 FB4_8 26 I/O I COMP0 FB4_9 27 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 16/20 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O I (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 2 I/O I (unused) 0 0 0 5 FB1_6 3 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 4 I/O I (unused) 0 0 0 5 FB1_9 5 GCK/I/O (unused) 0 0 0 5 FB1_10 (b) CT3<7> 3 0 0 2 FB1_11 6 GCK/I/O (b) CT3<0> 3 0 0 2 FB1_12 (b) (b) CT3<6> 4 0 0 1 FB1_13 (b) (b) CT3<1> 4 0 0 1 FB1_14 7 GCK/I/O (b) CT3A 2 0 0 3 FB1_15 8 I/O O CT3<5> 5 0 0 0 FB1_16 (b) (b) CT3B 3 0 0 2 FB1_17 9 I/O O CT3<2> 5 0 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: XBUS<3>.PIN 7: CT3<3> 12: ENABLE 2: XBUS<4>.PIN 8: CT3<4> 13: SEL_0 3: COMP3 9: CT3<5>.LFBK 14: SEL_1 4: CT3<0>.LFBK 10: CT3<6>.LFBK 15: SEL_2 5: CT3<1>.LFBK 11: CT3<7>.LFBK 16: XLXN_472.LFBK 6: CT3<2>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CT3<7> X.XXXXXXXXXXXXX......................... 14 14 CT3<0> X.XXXXXXXXXXXXX......................... 14 14 CT3<6> X.XXXXXXXXXXXXX......................... 14 14 CT3<1> X.XXXXXXXXXXXXX......................... 14 14 CT3A .XX........XXXX......................... 6 6 CT3<5> X.XXXXXXXXXXXXX......................... 14 14 CT3B .XX........XXXXX........................ 7 7 CT3<2> X.XXXXXXXXXXXXX......................... 14 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 30/6 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\2 3 FB2_1 (b) (b) XBUS<3> 5 0 0 0 FB2_2 35 I/O I/O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) XBUS<2> 5 0 0 0 FB2_5 36 I/O I/O XBUS<1> 5 0 0 0 FB2_6 37 I/O I/O (unused) 0 0 0 5 FB2_7 (b) XBUS<0> 5 0 0 0 FB2_8 38 I/O I/O (unused) 0 0 0 5 FB2_9 39 GSR/I/O CT0<7> 3 0 0 2 FB2_10 (b) (b) CT0<0> 3 0 0 2 FB2_11 40 GTS/I/O (b) CT0<6> 4 0 0 1 FB2_12 (b) (b) CT0<1> 4 0 0 1 FB2_13 (b) (b) CT0<5> 5 0 0 0 FB2_14 42 GTS/I/O GTS GTS_OUT 2 0 0 3 FB2_15 43 I/O O CT0<2> 5 0 0 0 FB2_16 (b) (b) CT0<4> 6 1<- 0 0 FB2_17 44 I/O (b) CT0<3> 6 2<- /\1 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: XBUS<0>.PIN 11: CT0A 21: CT2<2> 2: COMP0 12: CT0B 22: CT2<3> 3: CT0<0>.LFBK 13: CT1<0> 23: CT3<0> 4: CT0<1>.LFBK 14: CT1<1> 24: CT3<1> 5: CT0<2>.LFBK 15: CT1<2> 25: CT3<2> 6: CT0<3>.LFBK 16: CT1<3> 26: CT3<3> 7: CT0<4>.LFBK 17: CT1A 27: ENABLE 8: CT0<5>.LFBK 18: CT1B 28: SEL_0 9: CT0<6>.LFBK 19: CT2<0> 29: SEL_1 10: CT0<7>.LFBK 20: CT2<1> 30: SEL_2 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XBUS<3> .....X.........X.X...X...X.XXX.......... 8 8 XBUS<2> ....X.........X.X...X...X..XXX.......... 8 8 XBUS<1> ...X.......X.X.....X...X...XXX.......... 8 8 XBUS<0> ..X.......X.X.....X...X....XXX.......... 8 8 CT0<7> XXXXXXXXXX................XXXX.......... 14 14 CT0<0> XXXXXXXXXX................XXXX.......... 14 14 CT0<6> XXXXXXXXXX................XXXX.......... 14 14 CT0<1> XXXXXXXXXX................XXXX.......... 14 14 CT0<5> XXXXXXXXXX................XXXX.......... 14 14 GTS_OUT ..........................XXXX.......... 4 4 CT0<2> XXXXXXXXXX................XXXX.......... 14 14 CT0<4> XXXXXXXXXX................XXXX.......... 14 14 CT0<3> XXXXXXXXXX................XXXX.......... 14 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 30/6 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use CT2<7> 3 0 /\2 0 FB3_1 (b) (b) CT0A 2 0 0 3 FB3_2 11 I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) CT0B 3 0 0 2 FB3_5 12 I/O O CT2<0> 3 0 0 2 FB3_6 (b) (b) CT2<6> 4 0 0 1 FB3_7 (b) (b) CT1A 2 0 0 3 FB3_8 13 I/O O CT1B 3 0 0 2 FB3_9 14 I/O O CT2<1> 4 0 0 1 FB3_10 (b) (b) CT2A 2 0 0 3 FB3_11 18 I/O O CT2<5> 5 0 0 0 FB3_12 (b) (b) CT2<2> 5 0 0 0 FB3_13 (b) (b) CT2B 3 0 \/2 0 FB3_14 19 I/O O CT3<4> 6 2<- \/1 0 FB3_15 20 I/O (b) CT3<3> 6 1<- 0 0 FB3_16 (b) (b) CT2<4> 6 1<- 0 0 FB3_17 22 I/O (b) CT2<3> 6 2<- /\1 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: XBUS<2>.PIN 11: CT2<3>.LFBK 21: CT3<5> 2: XBUS<3>.PIN 12: CT2<4>.LFBK 22: CT3<6> 3: XBUS<4>.PIN 13: CT2<5>.LFBK 23: CT3<7> 4: COMP0 14: CT2<6>.LFBK 24: ENABLE 5: COMP1 15: CT2<7>.LFBK 25: SEL_0 6: COMP2 16: CT3<0> 26: SEL_1 7: COMP3 17: CT3<1> 27: SEL_2 8: CT2<0>.LFBK 18: CT3<2> 28: XLXN_473.LFBK 9: CT2<1>.LFBK 19: CT3<3>.LFBK 29: XLXN_474.LFBK 10: CT2<2>.LFBK 20: CT3<4>.LFBK 30: XLXN_475.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CT2<7> X....X.XXXXXXXX........XXXX............. 14 14 CT0A ..XX...................XXXX............. 6 6 CT0B ..XX...................XXXX..X.......... 7 7 CT2<0> X....X.XXXXXXXX........XXXX............. 14 14 CT2<6> X....X.XXXXXXXX........XXXX............. 14 14 CT1A ..X.X..................XXXX............. 6 6 CT1B ..X.X..................XXXX.X........... 7 7 CT2<1> X....X.XXXXXXXX........XXXX............. 14 14 CT2A ..X..X.................XXXX............. 6 6 CT2<5> X....X.XXXXXXXX........XXXX............. 14 14 CT2<2> X....X.XXXXXXXX........XXXX............. 14 14 CT2B ..X..X.................XXXXX............ 7 7 CT3<4> .X....X........XXXXXXXXXXXX............. 14 14 CT3<3> .X....X........XXXXXXXXXXXX............. 14 14 CT2<4> X....X.XXXXXXXX........XXXX............. 14 14 CT2<3> X....X.XXXXXXXX........XXXX............. 14 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 30/6 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\2 3 FB4_1 (b) (b) (unused) 0 0 0 5 FB4_2 24 I/O I (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 25 I/O I (unused) 0 0 0 5 FB4_6 (b) CT1<7> 3 0 0 2 FB4_7 (b) (b) CT1<0> 3 0 0 2 FB4_8 26 I/O I CT1<6> 4 0 0 1 FB4_9 27 I/O I CT1<1> 4 0 0 1 FB4_10 (b) (b) XBUS<7> 5 0 0 0 FB4_11 28 I/O O CT1<5> 5 0 0 0 FB4_12 (b) (b) CT1<2> 5 0 0 0 FB4_13 (b) (b) XBUS<6> 5 0 0 0 FB4_14 29 I/O O XBUS<5> 5 0 0 0 FB4_15 33 I/O O CT1<4> 6 1<- 0 0 FB4_16 (b) (b) XBUS<4> 5 1<- /\1 0 FB4_17 34 I/O I/O CT1<3> 6 2<- /\1 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: XBUS<1>.PIN 11: CT1<4>.LFBK 21: CT3<4> 2: COMP1 12: CT1<5>.LFBK 22: CT3<5> 3: CT0<4> 13: CT1<6>.LFBK 23: CT3<6> 4: CT0<5> 14: CT1<7>.LFBK 24: CT3<7> 5: CT0<6> 15: CT2<4> 25: CT3A 6: CT0<7> 16: CT2<5> 26: CT3B 7: CT1<0>.LFBK 17: CT2<6> 27: ENABLE 8: CT1<1>.LFBK 18: CT2<7> 28: SEL_0 9: CT1<2>.LFBK 19: CT2A 29: SEL_1 10: CT1<3>.LFBK 20: CT2B 30: SEL_2 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CT1<7> XX....XXXXXXXX............XXXX.......... 14 14 CT1<0> XX....XXXXXXXX............XXXX.......... 14 14 CT1<6> XX....XXXXXXXX............XXXX.......... 14 14 CT1<1> XX....XXXXXXXX............XXXX.......... 14 14 XBUS<7> .....X.......X...X.....X.X.XXX.......... 8 8 CT1<5> XX....XXXXXXXX............XXXX.......... 14 14 CT1<2> XX....XXXXXXXX............XXXX.......... 14 14 XBUS<6> ....X.......X...X.....X.X..XXX.......... 8 8 XBUS<5> ...X.......X...X...X.X.....XXX.......... 8 8 CT1<4> XX....XXXXXXXX............XXXX.......... 14 14 XBUS<4> ..X.......X...X...X.X......XXX.......... 8 8 CT1<3> XX....XXXXXXXX............XXXX.......... 14 14 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_CT00: FTCPE port map (CT0(0),CT0_T(0),COMP0,CT0_CLR(0),'0'); CT0_T(0) <= (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND CT0(7).LFBK); CT0_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT01: FTCPE port map (CT0(1),CT0_T(1),COMP0,CT0_CLR(1),'0'); CT0_T(1) <= ((NOT CT0(0).LFBK) OR (CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND CT0(7).LFBK)); CT0_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT02: FTCPE port map (CT0(2),CT0_T(2),COMP0,CT0_CLR(2),'0'); CT0_T(2) <= ((NOT CT0(0).LFBK) OR (NOT CT0(1).LFBK) OR (CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND CT0(7).LFBK)); CT0_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT03: FTCPE port map (CT0(3),CT0_T(3),COMP0,CT0_CLR(3),'0'); CT0_T(3) <= ((NOT CT0(2).LFBK) OR (CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND CT0(7).LFBK) OR (NOT CT0(0).LFBK) OR (NOT CT0(1).LFBK)); CT0_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT04: FTCPE port map (CT0(4),CT0_T(4),COMP0,CT0_CLR(4),'0'); CT0_T(4) <= ((CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND NOT CT0(7).LFBK) OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND NOT CT0(4).LFBK) OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND NOT CT0(5).LFBK) OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND NOT CT0(6).LFBK)); CT0_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT05: FTCPE port map (CT0(5),CT0_T(5),COMP0,CT0_CLR(5),'0'); CT0_T(5) <= ((CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND NOT CT0(5).LFBK) OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND NOT CT0(6).LFBK) OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND NOT CT0(7).LFBK)); CT0_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT06: FTCPE port map (CT0(6),CT0_T(6),COMP0,CT0_CLR(6),'0'); CT0_T(6) <= ((CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND NOT CT0(6).LFBK) OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND NOT CT0(7).LFBK)); CT0_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT07: FTCPE port map (CT0(7),CT0_T(7),COMP0,CT0_CLR(7),'0'); CT0_T(7) <= (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND NOT CT0(7).LFBK); CT0_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN); FTCPE_CT0A: FTCPE port map (CT0A,'1',COMP0,'0',CT0A_PRE); CT0A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT0B: FTCPE port map (CT0B,XLXN_475.LFBK,COMP0,'0',CT0B_PRE); CT0B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT10: FTCPE port map (CT1(0),CT1_T(0),COMP1,CT1_CLR(0),'0'); CT1_T(0) <= (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK); CT1_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT11: FTCPE port map (CT1(1),CT1_T(1),COMP1,CT1_CLR(1),'0'); CT1_T(1) <= ((NOT CT1(0).LFBK) OR (CT1(4).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK)); CT1_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT12: FTCPE port map (CT1(2),CT1_T(2),COMP1,CT1_CLR(2),'0'); CT1_T(2) <= ((NOT CT1(0).LFBK) OR (NOT CT1(1).LFBK) OR (CT1(4).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK)); CT1_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT13: FTCPE port map (CT1(3),CT1_T(3),COMP1,CT1_CLR(3),'0'); CT1_T(3) <= ((NOT CT1(2).LFBK) OR (CT1(4).LFBK AND CT1(3).LFBK AND CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK) OR (NOT CT1(0).LFBK) OR (NOT CT1(1).LFBK)); CT1_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT14: FTCPE port map (CT1(4),CT1_T(4),COMP1,CT1_CLR(4),'0'); CT1_T(4) <= ((CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK) OR (NOT CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK) OR (CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(5).LFBK) OR (CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(6).LFBK)); CT1_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT15: FTCPE port map (CT1(5),CT1_T(5),COMP1,CT1_CLR(5),'0'); CT1_T(5) <= ((CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK) OR (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(5).LFBK) OR (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(6).LFBK)); CT1_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT16: FTCPE port map (CT1(6),CT1_T(6),COMP1,CT1_CLR(6),'0'); CT1_T(6) <= ((CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK AND CT1(5).LFBK) OR (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND CT1(5).LFBK AND NOT CT1(6).LFBK)); CT1_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT17: FTCPE port map (CT1(7),CT1_T(7),COMP1,CT1_CLR(7),'0'); CT1_T(7) <= (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK); CT1_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN); FTCPE_CT1A: FTCPE port map (CT1A,'1',COMP1,'0',CT1A_PRE); CT1A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT1B: FTCPE port map (CT1B,XLXN_474.LFBK,COMP1,'0',CT1B_PRE); CT1B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT20: FTCPE port map (CT2(0),CT2_T(0),COMP2,CT2_CLR(0),'0'); CT2_T(0) <= (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND CT2(7).LFBK); CT2_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT21: FTCPE port map (CT2(1),CT2_T(1),COMP2,CT2_CLR(1),'0'); CT2_T(1) <= ((NOT CT2(0).LFBK) OR (CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND CT2(7).LFBK)); CT2_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT22: FTCPE port map (CT2(2),CT2_T(2),COMP2,CT2_CLR(2),'0'); CT2_T(2) <= ((NOT CT2(0).LFBK) OR (NOT CT2(1).LFBK) OR (CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND CT2(7).LFBK)); CT2_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT23: FTCPE port map (CT2(3),CT2_T(3),COMP2,CT2_CLR(3),'0'); CT2_T(3) <= ((NOT CT2(2).LFBK) OR (CT2(4).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND CT2(7).LFBK) OR (NOT CT2(0).LFBK) OR (NOT CT2(1).LFBK)); CT2_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT24: FTCPE port map (CT2(4),CT2_T(4),COMP2,CT2_CLR(4),'0'); CT2_T(4) <= ((CT2(0).LFBK AND CT2(1).LFBK AND CT2(2).LFBK AND CT2(3).LFBK AND NOT CT2(7).LFBK) OR (CT2(0).LFBK AND CT2(1).LFBK AND NOT CT2(4).LFBK AND CT2(2).LFBK AND CT2(3).LFBK) OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(2).LFBK AND NOT CT2(5).LFBK AND CT2(3).LFBK) OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(2).LFBK AND CT2(3).LFBK AND NOT CT2(6).LFBK)); CT2_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT25: FTCPE port map (CT2(5),CT2_T(5),COMP2,CT2_CLR(5),'0'); CT2_T(5) <= ((CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND NOT CT2(5).LFBK AND CT2(3).LFBK) OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(3).LFBK AND NOT CT2(6).LFBK) OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(3).LFBK AND NOT CT2(7).LFBK)); CT2_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT26: FTCPE port map (CT2(6),CT2_T(6),COMP2,CT2_CLR(6),'0'); CT2_T(6) <= ((CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND NOT CT2(6).LFBK) OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND NOT CT2(7).LFBK)); CT2_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT27: FTCPE port map (CT2(7),CT2_T(7),COMP2,CT2_CLR(7),'0'); CT2_T(7) <= (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND NOT CT2(7).LFBK); CT2_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN); FTCPE_CT2A: FTCPE port map (CT2A,'1',COMP2,'0',CT2A_PRE); CT2A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT2B: FTCPE port map (CT2B,XLXN_473.LFBK,COMP2,'0',CT2B_PRE); CT2B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT30: FTCPE port map (CT3(0),CT3_T(0),COMP3,CT3_CLR(0),'0'); CT3_T(0) <= (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND CT3(5).LFBK AND CT3(6).LFBK AND CT3(7).LFBK); CT3_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT31: FTCPE port map (CT3(1),CT3_T(1),COMP3,CT3_CLR(1),'0'); CT3_T(1) <= ((NOT CT3(0).LFBK) OR (CT3(4) AND CT3(3) AND CT3(1).LFBK AND CT3(2).LFBK AND CT3(5).LFBK AND CT3(6).LFBK AND CT3(7).LFBK)); CT3_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT32: FTCPE port map (CT3(2),CT3_T(2),COMP3,CT3_CLR(2),'0'); CT3_T(2) <= ((NOT CT3(0).LFBK) OR (NOT CT3(1).LFBK) OR (CT3(4) AND CT3(3) AND CT3(2).LFBK AND CT3(5).LFBK AND CT3(6).LFBK AND CT3(7).LFBK)); CT3_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT33: FTCPE port map (CT3(3),CT3_T(3),COMP3,CT3_CLR(3),'0'); CT3_T(3) <= ((NOT CT3(0)) OR (NOT CT3(1)) OR (NOT CT3(2)) OR (CT3(5) AND CT3(6) AND CT3(7) AND CT3(4).LFBK AND CT3(3).LFBK)); CT3_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT34: FTCPE port map (CT3(4),CT3_T(4),COMP3,CT3_CLR(4),'0'); CT3_T(4) <= ((CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(6) AND CT3(3).LFBK) OR (CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(7) AND CT3(3).LFBK) OR (CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(5) AND CT3(3).LFBK) OR (CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(4).LFBK AND CT3(3).LFBK)); CT3_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT35: FTCPE port map (CT3(5),CT3_T(5),COMP3,CT3_CLR(5),'0'); CT3_T(5) <= ((CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND NOT CT3(5).LFBK) OR (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND NOT CT3(6).LFBK) OR (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND NOT CT3(7).LFBK)); CT3_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT36: FTCPE port map (CT3(6),CT3_T(6),COMP3,CT3_CLR(6),'0'); CT3_T(6) <= ((CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND CT3(5).LFBK AND NOT CT3(6).LFBK) OR (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND CT3(5).LFBK AND NOT CT3(7).LFBK)); CT3_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT37: FTCPE port map (CT3(7),CT3_T(7),COMP3,CT3_CLR(7),'0'); CT3_T(7) <= (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND CT3(2).LFBK AND CT3(5).LFBK AND CT3(6).LFBK AND NOT CT3(7).LFBK); CT3_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN); FTCPE_CT3A: FTCPE port map (CT3A,'1',COMP3,'0',CT3A_PRE); CT3A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); FTCPE_CT3B: FTCPE port map (CT3B,XLXN_472.LFBK,COMP3,'0',CT3B_PRE); CT3B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN); GTS_OUT <= ((NOT ENABLE) OR (SEL_0 AND SEL_1 AND SEL_2)); XBUS_I(0) <= ((SEL_0 AND SEL_1 AND CT3(0)) OR (SEL_0 AND NOT SEL_1 AND CT1(0)) OR (NOT SEL_0 AND SEL_1 AND CT2(0)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT0A) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(0).LFBK)); XBUS(0) <= XBUS_I(0) when GTS_IN = '1' else 'Z'; XBUS_I(1) <= ((SEL_0 AND SEL_1 AND CT3(1)) OR (SEL_0 AND NOT SEL_1 AND CT1(1)) OR (NOT SEL_0 AND SEL_1 AND CT2(1)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT0B) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(1).LFBK)); XBUS(1) <= XBUS_I(1) when GTS_IN = '1' else 'Z'; XBUS_I(2) <= ((SEL_0 AND SEL_1 AND CT3(2)) OR (SEL_0 AND NOT SEL_1 AND CT1(2)) OR (NOT SEL_0 AND SEL_1 AND CT2(2)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT1A) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(2).LFBK)); XBUS(2) <= XBUS_I(2) when GTS_IN = '1' else 'Z'; XBUS_I(3) <= ((SEL_0 AND SEL_1 AND CT3(3)) OR (SEL_0 AND NOT SEL_1 AND CT1(3)) OR (NOT SEL_0 AND SEL_1 AND CT2(3)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT1B) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(3).LFBK)); XBUS(3) <= XBUS_I(3) when GTS_IN = '1' else 'Z'; XBUS_I(4) <= ((NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT2A) OR (SEL_0 AND SEL_1 AND CT3(4)) OR (SEL_0 AND NOT SEL_1 AND CT1(4).LFBK) OR (NOT SEL_0 AND SEL_1 AND CT2(4)) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(4))); XBUS(4) <= XBUS_I(4) when GTS_IN = '1' else 'Z'; XBUS_I(5) <= ((SEL_0 AND SEL_1 AND CT3(5)) OR (SEL_0 AND NOT SEL_1 AND CT1(5).LFBK) OR (NOT SEL_0 AND SEL_1 AND CT2(5)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT2B) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(5))); XBUS(5) <= XBUS_I(5) when GTS_IN = '1' else 'Z'; XBUS_I(6) <= ((SEL_0 AND SEL_1 AND CT3(6)) OR (SEL_0 AND NOT SEL_1 AND CT1(6).LFBK) OR (NOT SEL_0 AND SEL_1 AND CT2(6)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT3A) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(6))); XBUS(6) <= XBUS_I(6) when GTS_IN = '1' else 'Z'; XBUS_I(7) <= ((SEL_0 AND SEL_1 AND CT3(7)) OR (SEL_0 AND NOT SEL_1 AND CT1(7).LFBK) OR (NOT SEL_0 AND SEL_1 AND CT2(7)) OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT3B) OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(7))); XBUS(7) <= XBUS_I(7) when GTS_IN = '1' else 'Z'; Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572-7-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572-7-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ENABLE 23 GND 2 SEL_2 24 COMP3 3 SEL_1 25 COMP2 4 SEL_0 26 COMP1 5 TIE 27 COMP0 6 TIE 28 XBUS<7> 7 TIE 29 XBUS<6> 8 CT3A 30 TDO 9 CT3B 31 GND 10 GND 32 VCC 11 CT0A 33 XBUS<5> 12 CT0B 34 XBUS<4> 13 CT1A 35 XBUS<3> 14 CT1B 36 XBUS<2> 15 TDI 37 XBUS<1> 16 TMS 38 XBUS<0> 17 TCK 39 TIE 18 CT2A 40 TIE 19 CT2B 41 VCC 20 TIE 42 GTS_IN 21 VCC 43 GTS_OUT 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572-7-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25