Design Name | Zufall_01 |
Device, Speed (SpeedFile Version) | XC9572, -7 (3.0) |
Date Created | Thu Jun 18 10:09:10 2015 |
Created By | Timing Report Generator: version P.49d |
Copyright | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
---|
Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
---|---|
Min. Clock Period | 13.000 ns. |
Max. Clock Frequency (fSYSTEM) | 76.923 MHz. |
Limited by Cycle Time for COMP3 | |
Clock to Setup (tCYC) | 13.000 ns. |
Pad to Pad Delay (tPD) | 12.500 ns. |
Clock Pad to Output Pad Delay (tCO) | 24.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
TS1002 | 0.0 | 0.0 | 0 | 0 |
TS1003 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 13.0 | 260 | 260 |
AUTO_TS_P2P | 0.0 | 24.0 | 76 | 76 |
AUTO_TS_P2F | 0.0 | 5.5 | 40 | 40 |
AUTO_TS_F2P | 0.0 | 18.5 | 48 | 48 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CT3<0>.Q to CT3<4>.D | 0.000 | 13.000 | -13.000 |
CT3<1>.Q to CT3<4>.D | 0.000 | 13.000 | -13.000 |
CT3<2>.Q to CT3<4>.D | 0.000 | 13.000 | -13.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
COMP2 to XBUS<4> | 0.000 | 24.000 | -24.000 |
COMP0 to XBUS<0> | 0.000 | 23.000 | -23.000 |
COMP0 to XBUS<1> | 0.000 | 23.000 | -23.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
COMP0 to CT0<0>.CLKF | 0.000 | 5.500 | -5.500 |
COMP0 to CT0<1>.CLKF | 0.000 | 5.500 | -5.500 |
COMP0 to CT0<2>.CLKF | 0.000 | 5.500 | -5.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CT2A.Q to XBUS<4> | 0.000 | 18.500 | -18.500 |
CT0<4>.Q to XBUS<4> | 0.000 | 17.500 | -17.500 |
CT0<5>.Q to XBUS<5> | 0.000 | 17.500 | -17.500 |
Clock | fEXT (MHz) | Reason |
---|---|---|
COMP3 | 76.923 | Limited by Cycle Time for COMP3 |
COMP2 | 100.000 | Limited by Clock Pulse Width for COMP2 |
COMP1 | 100.000 | Limited by Clock Pulse Width for COMP1 |
COMP0 | 100.000 | Limited by Clock Pulse Width for COMP0 |
Destination Pad | Clock (edge) to Pad |
---|---|
XBUS<0> | 23.000 |
XBUS<1> | 23.000 |
XBUS<2> | 23.000 |
XBUS<3> | 23.000 |
XBUS<4> | 23.000 |
XBUS<5> | 23.000 |
XBUS<6> | 23.000 |
XBUS<7> | 23.000 |
CT3A | 12.500 |
CT3B | 12.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
XBUS<4> | 24.000 |
XBUS<0> | 23.000 |
XBUS<1> | 23.000 |
XBUS<2> | 23.000 |
XBUS<3> | 23.000 |
XBUS<5> | 23.000 |
XBUS<6> | 23.000 |
XBUS<7> | 23.000 |
CT2A | 12.500 |
CT2B | 12.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
XBUS<0> | 23.000 |
XBUS<1> | 23.000 |
XBUS<2> | 23.000 |
XBUS<3> | 23.000 |
XBUS<4> | 19.000 |
XBUS<5> | 19.000 |
XBUS<6> | 19.000 |
XBUS<7> | 19.000 |
CT1A | 12.500 |
CT1B | 12.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
XBUS<0> | 23.000 |
XBUS<1> | 23.000 |
XBUS<4> | 23.000 |
XBUS<5> | 23.000 |
XBUS<6> | 23.000 |
XBUS<7> | 23.000 |
XBUS<2> | 19.000 |
XBUS<3> | 19.000 |
CT0A | 12.500 |
CT0B | 12.500 |
Source | Destination | Delay |
---|---|---|
CT3<0>.Q | CT3<4>.D | 13.000 |
CT3<1>.Q | CT3<4>.D | 13.000 |
CT3<2>.Q | CT3<4>.D | 13.000 |
CT3<5>.Q | CT3<3>.D | 13.000 |
CT3<6>.Q | CT3<3>.D | 13.000 |
CT3<6>.Q | CT3<4>.D | 13.000 |
CT3<7>.Q | CT3<3>.D | 13.000 |
CT3<7>.Q | CT3<4>.D | 13.000 |
CT3<0>.Q | CT3<3>.D | 12.000 |
CT3<1>.Q | CT3<3>.D | 12.000 |
CT3<2>.Q | CT3<3>.D | 12.000 |
CT3<3>.Q | CT3<0>.D | 12.000 |
CT3<3>.Q | CT3<1>.D | 12.000 |
CT3<3>.Q | CT3<2>.D | 12.000 |
CT3<3>.Q | CT3<5>.D | 12.000 |
CT3<3>.Q | CT3<6>.D | 12.000 |
CT3<3>.Q | CT3<7>.D | 12.000 |
CT3<4>.Q | CT3<0>.D | 12.000 |
CT3<4>.Q | CT3<1>.D | 12.000 |
CT3<4>.Q | CT3<2>.D | 12.000 |
CT3<4>.Q | CT3<5>.D | 12.000 |
CT3<4>.Q | CT3<6>.D | 12.000 |
CT3<4>.Q | CT3<7>.D | 12.000 |
CT3<5>.Q | CT3<4>.D | 12.000 |
CT3<3>.Q | CT3<3>.D | 9.000 |
CT3<3>.Q | CT3<4>.D | 9.000 |
CT3<4>.Q | CT3<3>.D | 9.000 |
CT3<0>.Q | CT3<0>.D | 8.000 |
CT3<0>.Q | CT3<1>.D | 8.000 |
CT3<0>.Q | CT3<2>.D | 8.000 |
CT3<0>.Q | CT3<5>.D | 8.000 |
CT3<0>.Q | CT3<6>.D | 8.000 |
CT3<0>.Q | CT3<7>.D | 8.000 |
CT3<1>.Q | CT3<0>.D | 8.000 |
CT3<1>.Q | CT3<1>.D | 8.000 |
CT3<1>.Q | CT3<2>.D | 8.000 |
CT3<1>.Q | CT3<5>.D | 8.000 |
CT3<1>.Q | CT3<6>.D | 8.000 |
CT3<1>.Q | CT3<7>.D | 8.000 |
CT3<2>.Q | CT3<0>.D | 8.000 |
CT3<2>.Q | CT3<1>.D | 8.000 |
CT3<2>.Q | CT3<2>.D | 8.000 |
CT3<2>.Q | CT3<5>.D | 8.000 |
CT3<2>.Q | CT3<6>.D | 8.000 |
CT3<2>.Q | CT3<7>.D | 8.000 |
CT3<4>.Q | CT3<4>.D | 8.000 |
CT3<5>.Q | CT3<0>.D | 8.000 |
CT3<5>.Q | CT3<1>.D | 8.000 |
CT3<5>.Q | CT3<2>.D | 8.000 |
CT3<5>.Q | CT3<5>.D | 8.000 |
CT3<5>.Q | CT3<6>.D | 8.000 |
CT3<5>.Q | CT3<7>.D | 8.000 |
CT3<6>.Q | CT3<0>.D | 8.000 |
CT3<6>.Q | CT3<1>.D | 8.000 |
CT3<6>.Q | CT3<2>.D | 8.000 |
CT3<6>.Q | CT3<5>.D | 8.000 |
CT3<6>.Q | CT3<6>.D | 8.000 |
CT3<6>.Q | CT3<7>.D | 8.000 |
CT3<7>.Q | CT3<0>.D | 8.000 |
CT3<7>.Q | CT3<1>.D | 8.000 |
CT3<7>.Q | CT3<2>.D | 8.000 |
CT3<7>.Q | CT3<5>.D | 8.000 |
CT3<7>.Q | CT3<6>.D | 8.000 |
CT3<7>.Q | CT3<7>.D | 8.000 |
CT3A.Q | CT3B.D | 8.000 |
Source | Destination | Delay |
---|---|---|
CT2<0>.Q | CT2<4>.D | 9.000 |
CT2<1>.Q | CT2<4>.D | 9.000 |
CT2<2>.Q | CT2<3>.D | 9.000 |
CT2<2>.Q | CT2<4>.D | 9.000 |
CT2<3>.Q | CT2<3>.D | 9.000 |
CT2<3>.Q | CT2<4>.D | 9.000 |
CT2<4>.Q | CT2<3>.D | 9.000 |
CT2<5>.Q | CT2<3>.D | 9.000 |
CT2<6>.Q | CT2<3>.D | 9.000 |
CT2<7>.Q | CT2<3>.D | 9.000 |
CT2<7>.Q | CT2<4>.D | 9.000 |
CT2<0>.Q | CT2<0>.D | 8.000 |
CT2<0>.Q | CT2<1>.D | 8.000 |
CT2<0>.Q | CT2<2>.D | 8.000 |
CT2<0>.Q | CT2<3>.D | 8.000 |
CT2<0>.Q | CT2<5>.D | 8.000 |
CT2<0>.Q | CT2<6>.D | 8.000 |
CT2<0>.Q | CT2<7>.D | 8.000 |
CT2<1>.Q | CT2<0>.D | 8.000 |
CT2<1>.Q | CT2<1>.D | 8.000 |
CT2<1>.Q | CT2<2>.D | 8.000 |
CT2<1>.Q | CT2<3>.D | 8.000 |
CT2<1>.Q | CT2<5>.D | 8.000 |
CT2<1>.Q | CT2<6>.D | 8.000 |
CT2<1>.Q | CT2<7>.D | 8.000 |
CT2<2>.Q | CT2<0>.D | 8.000 |
CT2<2>.Q | CT2<1>.D | 8.000 |
CT2<2>.Q | CT2<2>.D | 8.000 |
CT2<2>.Q | CT2<5>.D | 8.000 |
CT2<2>.Q | CT2<6>.D | 8.000 |
CT2<2>.Q | CT2<7>.D | 8.000 |
CT2<3>.Q | CT2<0>.D | 8.000 |
CT2<3>.Q | CT2<1>.D | 8.000 |
CT2<3>.Q | CT2<2>.D | 8.000 |
CT2<3>.Q | CT2<5>.D | 8.000 |
CT2<3>.Q | CT2<6>.D | 8.000 |
CT2<3>.Q | CT2<7>.D | 8.000 |
CT2<4>.Q | CT2<0>.D | 8.000 |
CT2<4>.Q | CT2<1>.D | 8.000 |
CT2<4>.Q | CT2<2>.D | 8.000 |
CT2<4>.Q | CT2<4>.D | 8.000 |
CT2<4>.Q | CT2<5>.D | 8.000 |
CT2<4>.Q | CT2<6>.D | 8.000 |
CT2<4>.Q | CT2<7>.D | 8.000 |
CT2<5>.Q | CT2<0>.D | 8.000 |
CT2<5>.Q | CT2<1>.D | 8.000 |
CT2<5>.Q | CT2<2>.D | 8.000 |
CT2<5>.Q | CT2<4>.D | 8.000 |
CT2<5>.Q | CT2<5>.D | 8.000 |
CT2<5>.Q | CT2<6>.D | 8.000 |
CT2<5>.Q | CT2<7>.D | 8.000 |
CT2<6>.Q | CT2<0>.D | 8.000 |
CT2<6>.Q | CT2<1>.D | 8.000 |
CT2<6>.Q | CT2<2>.D | 8.000 |
CT2<6>.Q | CT2<4>.D | 8.000 |
CT2<6>.Q | CT2<5>.D | 8.000 |
CT2<6>.Q | CT2<6>.D | 8.000 |
CT2<6>.Q | CT2<7>.D | 8.000 |
CT2<7>.Q | CT2<0>.D | 8.000 |
CT2<7>.Q | CT2<1>.D | 8.000 |
CT2<7>.Q | CT2<2>.D | 8.000 |
CT2<7>.Q | CT2<5>.D | 8.000 |
CT2<7>.Q | CT2<6>.D | 8.000 |
CT2<7>.Q | CT2<7>.D | 8.000 |
CT2A.Q | CT2B.D | 8.000 |
Source | Destination | Delay |
---|---|---|
CT1<0>.Q | CT1<4>.D | 9.000 |
CT1<1>.Q | CT1<4>.D | 9.000 |
CT1<2>.Q | CT1<3>.D | 9.000 |
CT1<2>.Q | CT1<4>.D | 9.000 |
CT1<3>.Q | CT1<3>.D | 9.000 |
CT1<3>.Q | CT1<4>.D | 9.000 |
CT1<4>.Q | CT1<3>.D | 9.000 |
CT1<5>.Q | CT1<3>.D | 9.000 |
CT1<6>.Q | CT1<3>.D | 9.000 |
CT1<7>.Q | CT1<3>.D | 9.000 |
CT1<7>.Q | CT1<4>.D | 9.000 |
CT1<0>.Q | CT1<0>.D | 8.000 |
CT1<0>.Q | CT1<1>.D | 8.000 |
CT1<0>.Q | CT1<2>.D | 8.000 |
CT1<0>.Q | CT1<3>.D | 8.000 |
CT1<0>.Q | CT1<5>.D | 8.000 |
CT1<0>.Q | CT1<6>.D | 8.000 |
CT1<0>.Q | CT1<7>.D | 8.000 |
CT1<1>.Q | CT1<0>.D | 8.000 |
CT1<1>.Q | CT1<1>.D | 8.000 |
CT1<1>.Q | CT1<2>.D | 8.000 |
CT1<1>.Q | CT1<3>.D | 8.000 |
CT1<1>.Q | CT1<5>.D | 8.000 |
CT1<1>.Q | CT1<6>.D | 8.000 |
CT1<1>.Q | CT1<7>.D | 8.000 |
CT1<2>.Q | CT1<0>.D | 8.000 |
CT1<2>.Q | CT1<1>.D | 8.000 |
CT1<2>.Q | CT1<2>.D | 8.000 |
CT1<2>.Q | CT1<5>.D | 8.000 |
CT1<2>.Q | CT1<6>.D | 8.000 |
CT1<2>.Q | CT1<7>.D | 8.000 |
CT1<3>.Q | CT1<0>.D | 8.000 |
CT1<3>.Q | CT1<1>.D | 8.000 |
CT1<3>.Q | CT1<2>.D | 8.000 |
CT1<3>.Q | CT1<5>.D | 8.000 |
CT1<3>.Q | CT1<6>.D | 8.000 |
CT1<3>.Q | CT1<7>.D | 8.000 |
CT1<4>.Q | CT1<0>.D | 8.000 |
CT1<4>.Q | CT1<1>.D | 8.000 |
CT1<4>.Q | CT1<2>.D | 8.000 |
CT1<4>.Q | CT1<4>.D | 8.000 |
CT1<4>.Q | CT1<5>.D | 8.000 |
CT1<4>.Q | CT1<6>.D | 8.000 |
CT1<4>.Q | CT1<7>.D | 8.000 |
CT1<5>.Q | CT1<0>.D | 8.000 |
CT1<5>.Q | CT1<1>.D | 8.000 |
CT1<5>.Q | CT1<2>.D | 8.000 |
CT1<5>.Q | CT1<4>.D | 8.000 |
CT1<5>.Q | CT1<5>.D | 8.000 |
CT1<5>.Q | CT1<6>.D | 8.000 |
CT1<5>.Q | CT1<7>.D | 8.000 |
CT1<6>.Q | CT1<0>.D | 8.000 |
CT1<6>.Q | CT1<1>.D | 8.000 |
CT1<6>.Q | CT1<2>.D | 8.000 |
CT1<6>.Q | CT1<4>.D | 8.000 |
CT1<6>.Q | CT1<5>.D | 8.000 |
CT1<6>.Q | CT1<6>.D | 8.000 |
CT1<6>.Q | CT1<7>.D | 8.000 |
CT1<7>.Q | CT1<0>.D | 8.000 |
CT1<7>.Q | CT1<1>.D | 8.000 |
CT1<7>.Q | CT1<2>.D | 8.000 |
CT1<7>.Q | CT1<5>.D | 8.000 |
CT1<7>.Q | CT1<6>.D | 8.000 |
CT1<7>.Q | CT1<7>.D | 8.000 |
CT1A.Q | CT1B.D | 8.000 |
Source | Destination | Delay |
---|---|---|
CT0<0>.Q | CT0<4>.D | 9.000 |
CT0<1>.Q | CT0<4>.D | 9.000 |
CT0<2>.Q | CT0<3>.D | 9.000 |
CT0<2>.Q | CT0<4>.D | 9.000 |
CT0<3>.Q | CT0<3>.D | 9.000 |
CT0<3>.Q | CT0<4>.D | 9.000 |
CT0<4>.Q | CT0<3>.D | 9.000 |
CT0<5>.Q | CT0<3>.D | 9.000 |
CT0<6>.Q | CT0<3>.D | 9.000 |
CT0<7>.Q | CT0<3>.D | 9.000 |
CT0<7>.Q | CT0<4>.D | 9.000 |
CT0<0>.Q | CT0<0>.D | 8.000 |
CT0<0>.Q | CT0<1>.D | 8.000 |
CT0<0>.Q | CT0<2>.D | 8.000 |
CT0<0>.Q | CT0<3>.D | 8.000 |
CT0<0>.Q | CT0<5>.D | 8.000 |
CT0<0>.Q | CT0<6>.D | 8.000 |
CT0<0>.Q | CT0<7>.D | 8.000 |
CT0<1>.Q | CT0<0>.D | 8.000 |
CT0<1>.Q | CT0<1>.D | 8.000 |
CT0<1>.Q | CT0<2>.D | 8.000 |
CT0<1>.Q | CT0<3>.D | 8.000 |
CT0<1>.Q | CT0<5>.D | 8.000 |
CT0<1>.Q | CT0<6>.D | 8.000 |
CT0<1>.Q | CT0<7>.D | 8.000 |
CT0<2>.Q | CT0<0>.D | 8.000 |
CT0<2>.Q | CT0<1>.D | 8.000 |
CT0<2>.Q | CT0<2>.D | 8.000 |
CT0<2>.Q | CT0<5>.D | 8.000 |
CT0<2>.Q | CT0<6>.D | 8.000 |
CT0<2>.Q | CT0<7>.D | 8.000 |
CT0<3>.Q | CT0<0>.D | 8.000 |
CT0<3>.Q | CT0<1>.D | 8.000 |
CT0<3>.Q | CT0<2>.D | 8.000 |
CT0<3>.Q | CT0<5>.D | 8.000 |
CT0<3>.Q | CT0<6>.D | 8.000 |
CT0<3>.Q | CT0<7>.D | 8.000 |
CT0<4>.Q | CT0<0>.D | 8.000 |
CT0<4>.Q | CT0<1>.D | 8.000 |
CT0<4>.Q | CT0<2>.D | 8.000 |
CT0<4>.Q | CT0<4>.D | 8.000 |
CT0<4>.Q | CT0<5>.D | 8.000 |
CT0<4>.Q | CT0<6>.D | 8.000 |
CT0<4>.Q | CT0<7>.D | 8.000 |
CT0<5>.Q | CT0<0>.D | 8.000 |
CT0<5>.Q | CT0<1>.D | 8.000 |
CT0<5>.Q | CT0<2>.D | 8.000 |
CT0<5>.Q | CT0<4>.D | 8.000 |
CT0<5>.Q | CT0<5>.D | 8.000 |
CT0<5>.Q | CT0<6>.D | 8.000 |
CT0<5>.Q | CT0<7>.D | 8.000 |
CT0<6>.Q | CT0<0>.D | 8.000 |
CT0<6>.Q | CT0<1>.D | 8.000 |
CT0<6>.Q | CT0<2>.D | 8.000 |
CT0<6>.Q | CT0<4>.D | 8.000 |
CT0<6>.Q | CT0<5>.D | 8.000 |
CT0<6>.Q | CT0<6>.D | 8.000 |
CT0<6>.Q | CT0<7>.D | 8.000 |
CT0<7>.Q | CT0<0>.D | 8.000 |
CT0<7>.Q | CT0<1>.D | 8.000 |
CT0<7>.Q | CT0<2>.D | 8.000 |
CT0<7>.Q | CT0<5>.D | 8.000 |
CT0<7>.Q | CT0<6>.D | 8.000 |
CT0<7>.Q | CT0<7>.D | 8.000 |
CT0A.Q | CT0B.D | 8.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
SEL_0 | XBUS<4> | 12.500 |
SEL_1 | XBUS<4> | 12.500 |
SEL_2 | XBUS<4> | 12.500 |
ENABLE | GTS_OUT | 11.500 |
SEL_0 | GTS_OUT | 11.500 |
SEL_0 | XBUS<0> | 11.500 |
SEL_0 | XBUS<1> | 11.500 |
SEL_0 | XBUS<2> | 11.500 |
SEL_0 | XBUS<3> | 11.500 |
SEL_0 | XBUS<5> | 11.500 |
SEL_0 | XBUS<6> | 11.500 |
SEL_0 | XBUS<7> | 11.500 |
SEL_1 | GTS_OUT | 11.500 |
SEL_1 | XBUS<0> | 11.500 |
SEL_1 | XBUS<1> | 11.500 |
SEL_1 | XBUS<2> | 11.500 |
SEL_1 | XBUS<3> | 11.500 |
SEL_1 | XBUS<5> | 11.500 |
SEL_1 | XBUS<6> | 11.500 |
SEL_1 | XBUS<7> | 11.500 |
SEL_2 | GTS_OUT | 11.500 |
SEL_2 | XBUS<0> | 11.500 |
SEL_2 | XBUS<1> | 11.500 |
SEL_2 | XBUS<2> | 11.500 |
SEL_2 | XBUS<3> | 11.500 |
SEL_2 | XBUS<5> | 11.500 |
SEL_2 | XBUS<6> | 11.500 |
SEL_2 | XBUS<7> | 11.500 |
GTS_IN | XBUS<0> | 5.500 |
GTS_IN | XBUS<1> | 5.500 |
GTS_IN | XBUS<2> | 5.500 |
GTS_IN | XBUS<3> | 5.500 |
GTS_IN | XBUS<4> | 5.500 |
GTS_IN | XBUS<5> | 5.500 |
GTS_IN | XBUS<6> | 5.500 |
GTS_IN | XBUS<7> | 5.500 |