Equations

********** Mapped Logic **********
FTCPE_CT00: FTCPE port map (CT0(0),CT0_T(0),COMP0,CT0_CLR(0),'0');
     CT0_T(0) <= (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND
      CT0(7).LFBK);
     CT0_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT01: FTCPE port map (CT0(1),CT0_T(1),COMP0,CT0_CLR(1),'0');
     CT0_T(1) <= ((NOT CT0(0).LFBK)
      OR (CT0(1).LFBK AND CT0(2).LFBK AND CT0(3).LFBK AND
      CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND CT0(7).LFBK));
     CT0_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT02: FTCPE port map (CT0(2),CT0_T(2),COMP0,CT0_CLR(2),'0');
     CT0_T(2) <= ((NOT CT0(0).LFBK)
      OR (NOT CT0(1).LFBK)
      OR (CT0(2).LFBK AND CT0(3).LFBK AND CT0(4).LFBK AND
      CT0(5).LFBK AND CT0(6).LFBK AND CT0(7).LFBK));
     CT0_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT03: FTCPE port map (CT0(3),CT0_T(3),COMP0,CT0_CLR(3),'0');
     CT0_T(3) <= ((NOT CT0(2).LFBK)
      OR (CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND
      CT0(6).LFBK AND CT0(7).LFBK)
      OR (NOT CT0(0).LFBK)
      OR (NOT CT0(1).LFBK));
     CT0_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT04: FTCPE port map (CT0(4),CT0_T(4),COMP0,CT0_CLR(4),'0');
     CT0_T(4) <= ((CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND NOT CT0(7).LFBK)
      OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND NOT CT0(4).LFBK)
      OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND NOT CT0(5).LFBK)
      OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND NOT CT0(6).LFBK));
     CT0_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT05: FTCPE port map (CT0(5),CT0_T(5),COMP0,CT0_CLR(5),'0');
     CT0_T(5) <= ((CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND NOT CT0(5).LFBK)
      OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND NOT CT0(6).LFBK)
      OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND NOT CT0(7).LFBK));
     CT0_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT06: FTCPE port map (CT0(6),CT0_T(6),COMP0,CT0_CLR(6),'0');
     CT0_T(6) <= ((CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND NOT CT0(6).LFBK)
      OR (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND NOT CT0(7).LFBK));
     CT0_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT07: FTCPE port map (CT0(7),CT0_T(7),COMP0,CT0_CLR(7),'0');
     CT0_T(7) <= (CT0(0).LFBK AND CT0(1).LFBK AND CT0(2).LFBK AND
      CT0(3).LFBK AND CT0(4).LFBK AND CT0(5).LFBK AND CT0(6).LFBK AND
      NOT CT0(7).LFBK);
     CT0_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(0).PIN);
FTCPE_CT0A: FTCPE port map (CT0A,'1',COMP0,'0',CT0A_PRE);
     CT0A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT0B: FTCPE port map (CT0B,XLXN_475.LFBK,COMP0,'0',CT0B_PRE);
     CT0B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT10: FTCPE port map (CT1(0),CT1_T(0),COMP1,CT1_CLR(0),'0');
     CT1_T(0) <= (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND CT1(7).LFBK AND CT1(5).LFBK AND
      CT1(6).LFBK);
     CT1_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT11: FTCPE port map (CT1(1),CT1_T(1),COMP1,CT1_CLR(1),'0');
     CT1_T(1) <= ((NOT CT1(0).LFBK)
      OR (CT1(4).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND
      CT1(3).LFBK AND CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK));
     CT1_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT12: FTCPE port map (CT1(2),CT1_T(2),COMP1,CT1_CLR(2),'0');
     CT1_T(2) <= ((NOT CT1(0).LFBK)
      OR (NOT CT1(1).LFBK)
      OR (CT1(4).LFBK AND CT1(2).LFBK AND CT1(3).LFBK AND
      CT1(7).LFBK AND CT1(5).LFBK AND CT1(6).LFBK));
     CT1_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT13: FTCPE port map (CT1(3),CT1_T(3),COMP1,CT1_CLR(3),'0');
     CT1_T(3) <= ((NOT CT1(2).LFBK)
      OR (CT1(4).LFBK AND CT1(3).LFBK AND CT1(7).LFBK AND
      CT1(5).LFBK AND CT1(6).LFBK)
      OR (NOT CT1(0).LFBK)
      OR (NOT CT1(1).LFBK));
     CT1_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT14: FTCPE port map (CT1(4),CT1_T(4),COMP1,CT1_CLR(4),'0');
     CT1_T(4) <= ((CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND
      CT1(3).LFBK AND NOT CT1(7).LFBK)
      OR (NOT CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK)
      OR (CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND
      CT1(3).LFBK AND NOT CT1(5).LFBK)
      OR (CT1(0).LFBK AND CT1(1).LFBK AND CT1(2).LFBK AND
      CT1(3).LFBK AND NOT CT1(6).LFBK));
     CT1_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT15: FTCPE port map (CT1(5),CT1_T(5),COMP1,CT1_CLR(5),'0');
     CT1_T(5) <= ((CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK)
      OR (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(5).LFBK)
      OR (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(6).LFBK));
     CT1_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT16: FTCPE port map (CT1(6),CT1_T(6),COMP1,CT1_CLR(6),'0');
     CT1_T(6) <= ((CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK AND CT1(5).LFBK)
      OR (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND CT1(5).LFBK AND NOT CT1(6).LFBK));
     CT1_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT17: FTCPE port map (CT1(7),CT1_T(7),COMP1,CT1_CLR(7),'0');
     CT1_T(7) <= (CT1(4).LFBK AND CT1(0).LFBK AND CT1(1).LFBK AND
      CT1(2).LFBK AND CT1(3).LFBK AND NOT CT1(7).LFBK AND CT1(5).LFBK AND
      CT1(6).LFBK);
     CT1_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(1).PIN);
FTCPE_CT1A: FTCPE port map (CT1A,'1',COMP1,'0',CT1A_PRE);
     CT1A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT1B: FTCPE port map (CT1B,XLXN_474.LFBK,COMP1,'0',CT1B_PRE);
     CT1B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT20: FTCPE port map (CT2(0),CT2_T(0),COMP2,CT2_CLR(0),'0');
     CT2_T(0) <= (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND
      CT2(7).LFBK);
     CT2_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT21: FTCPE port map (CT2(1),CT2_T(1),COMP2,CT2_CLR(1),'0');
     CT2_T(1) <= ((NOT CT2(0).LFBK)
      OR (CT2(1).LFBK AND CT2(4).LFBK AND CT2(2).LFBK AND
      CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND CT2(7).LFBK));
     CT2_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT22: FTCPE port map (CT2(2),CT2_T(2),COMP2,CT2_CLR(2),'0');
     CT2_T(2) <= ((NOT CT2(0).LFBK)
      OR (NOT CT2(1).LFBK)
      OR (CT2(4).LFBK AND CT2(2).LFBK AND CT2(5).LFBK AND
      CT2(3).LFBK AND CT2(6).LFBK AND CT2(7).LFBK));
     CT2_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT23: FTCPE port map (CT2(3),CT2_T(3),COMP2,CT2_CLR(3),'0');
     CT2_T(3) <= ((NOT CT2(2).LFBK)
      OR (CT2(4).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND
      CT2(6).LFBK AND CT2(7).LFBK)
      OR (NOT CT2(0).LFBK)
      OR (NOT CT2(1).LFBK));
     CT2_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT24: FTCPE port map (CT2(4),CT2_T(4),COMP2,CT2_CLR(4),'0');
     CT2_T(4) <= ((CT2(0).LFBK AND CT2(1).LFBK AND CT2(2).LFBK AND
      CT2(3).LFBK AND NOT CT2(7).LFBK)
      OR (CT2(0).LFBK AND CT2(1).LFBK AND NOT CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(3).LFBK)
      OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(2).LFBK AND
      NOT CT2(5).LFBK AND CT2(3).LFBK)
      OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(2).LFBK AND
      CT2(3).LFBK AND NOT CT2(6).LFBK));
     CT2_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT25: FTCPE port map (CT2(5),CT2_T(5),COMP2,CT2_CLR(5),'0');
     CT2_T(5) <= ((CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND NOT CT2(5).LFBK AND CT2(3).LFBK)
      OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(3).LFBK AND NOT CT2(6).LFBK)
      OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(3).LFBK AND NOT CT2(7).LFBK));
     CT2_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT26: FTCPE port map (CT2(6),CT2_T(6),COMP2,CT2_CLR(6),'0');
     CT2_T(6) <= ((CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND NOT CT2(6).LFBK)
      OR (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND NOT CT2(7).LFBK));
     CT2_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT27: FTCPE port map (CT2(7),CT2_T(7),COMP2,CT2_CLR(7),'0');
     CT2_T(7) <= (CT2(0).LFBK AND CT2(1).LFBK AND CT2(4).LFBK AND
      CT2(2).LFBK AND CT2(5).LFBK AND CT2(3).LFBK AND CT2(6).LFBK AND
      NOT CT2(7).LFBK);
     CT2_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(2).PIN);
FTCPE_CT2A: FTCPE port map (CT2A,'1',COMP2,'0',CT2A_PRE);
     CT2A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT2B: FTCPE port map (CT2B,XLXN_473.LFBK,COMP2,'0',CT2B_PRE);
     CT2B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT30: FTCPE port map (CT3(0),CT3_T(0),COMP3,CT3_CLR(0),'0');
     CT3_T(0) <= (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND CT3(5).LFBK AND CT3(6).LFBK AND CT3(7).LFBK);
     CT3_CLR(0) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT31: FTCPE port map (CT3(1),CT3_T(1),COMP3,CT3_CLR(1),'0');
     CT3_T(1) <= ((NOT CT3(0).LFBK)
      OR (CT3(4) AND CT3(3) AND CT3(1).LFBK AND CT3(2).LFBK AND
      CT3(5).LFBK AND CT3(6).LFBK AND CT3(7).LFBK));
     CT3_CLR(1) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT32: FTCPE port map (CT3(2),CT3_T(2),COMP3,CT3_CLR(2),'0');
     CT3_T(2) <= ((NOT CT3(0).LFBK)
      OR (NOT CT3(1).LFBK)
      OR (CT3(4) AND CT3(3) AND CT3(2).LFBK AND CT3(5).LFBK AND
      CT3(6).LFBK AND CT3(7).LFBK));
     CT3_CLR(2) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT33: FTCPE port map (CT3(3),CT3_T(3),COMP3,CT3_CLR(3),'0');
     CT3_T(3) <= ((NOT CT3(0))
      OR (NOT CT3(1))
      OR (NOT CT3(2))
      OR (CT3(5) AND CT3(6) AND CT3(7) AND CT3(4).LFBK AND
      CT3(3).LFBK));
     CT3_CLR(3) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT34: FTCPE port map (CT3(4),CT3_T(4),COMP3,CT3_CLR(4),'0');
     CT3_T(4) <= ((CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(6) AND
      CT3(3).LFBK)
      OR (CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(7) AND
      CT3(3).LFBK)
      OR (CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(5) AND
      CT3(3).LFBK)
      OR (CT3(0) AND CT3(1) AND CT3(2) AND NOT CT3(4).LFBK AND
      CT3(3).LFBK));
     CT3_CLR(4) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT35: FTCPE port map (CT3(5),CT3_T(5),COMP3,CT3_CLR(5),'0');
     CT3_T(5) <= ((CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND NOT CT3(5).LFBK)
      OR (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND NOT CT3(6).LFBK)
      OR (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND NOT CT3(7).LFBK));
     CT3_CLR(5) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT36: FTCPE port map (CT3(6),CT3_T(6),COMP3,CT3_CLR(6),'0');
     CT3_T(6) <= ((CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND CT3(5).LFBK AND NOT CT3(6).LFBK)
      OR (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND CT3(5).LFBK AND NOT CT3(7).LFBK));
     CT3_CLR(6) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT37: FTCPE port map (CT3(7),CT3_T(7),COMP3,CT3_CLR(7),'0');
     CT3_T(7) <= (CT3(4) AND CT3(3) AND CT3(0).LFBK AND CT3(1).LFBK AND
      CT3(2).LFBK AND CT3(5).LFBK AND CT3(6).LFBK AND NOT CT3(7).LFBK);
     CT3_CLR(7) <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(3).PIN);
FTCPE_CT3A: FTCPE port map (CT3A,'1',COMP3,'0',CT3A_PRE);
     CT3A_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
FTCPE_CT3B: FTCPE port map (CT3B,XLXN_472.LFBK,COMP3,'0',CT3B_PRE);
     CT3B_PRE <= (SEL_0 AND SEL_1 AND SEL_2 AND ENABLE AND XBUS(4).PIN);
GTS_OUT <= ((NOT ENABLE)
      OR (SEL_0 AND SEL_1 AND SEL_2));
XBUS_I(0) <= ((SEL_0 AND SEL_1 AND CT3(0))
      OR (SEL_0 AND NOT SEL_1 AND CT1(0))
      OR (NOT SEL_0 AND SEL_1 AND CT2(0))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT0A)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(0).LFBK));
     XBUS(0) <= XBUS_I(0) when GTS_IN = '1' else 'Z';
XBUS_I(1) <= ((SEL_0 AND SEL_1 AND CT3(1))
      OR (SEL_0 AND NOT SEL_1 AND CT1(1))
      OR (NOT SEL_0 AND SEL_1 AND CT2(1))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT0B)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(1).LFBK));
     XBUS(1) <= XBUS_I(1) when GTS_IN = '1' else 'Z';
XBUS_I(2) <= ((SEL_0 AND SEL_1 AND CT3(2))
      OR (SEL_0 AND NOT SEL_1 AND CT1(2))
      OR (NOT SEL_0 AND SEL_1 AND CT2(2))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT1A)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(2).LFBK));
     XBUS(2) <= XBUS_I(2) when GTS_IN = '1' else 'Z';
XBUS_I(3) <= ((SEL_0 AND SEL_1 AND CT3(3))
      OR (SEL_0 AND NOT SEL_1 AND CT1(3))
      OR (NOT SEL_0 AND SEL_1 AND CT2(3))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT1B)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(3).LFBK));
     XBUS(3) <= XBUS_I(3) when GTS_IN = '1' else 'Z';
XBUS_I(4) <= ((NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT2A)
      OR (SEL_0 AND SEL_1 AND CT3(4))
      OR (SEL_0 AND NOT SEL_1 AND CT1(4).LFBK)
      OR (NOT SEL_0 AND SEL_1 AND CT2(4))
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(4)));
     XBUS(4) <= XBUS_I(4) when GTS_IN = '1' else 'Z';
XBUS_I(5) <= ((SEL_0 AND SEL_1 AND CT3(5))
      OR (SEL_0 AND NOT SEL_1 AND CT1(5).LFBK)
      OR (NOT SEL_0 AND SEL_1 AND CT2(5))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT2B)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(5)));
     XBUS(5) <= XBUS_I(5) when GTS_IN = '1' else 'Z';
XBUS_I(6) <= ((SEL_0 AND SEL_1 AND CT3(6))
      OR (SEL_0 AND NOT SEL_1 AND CT1(6).LFBK)
      OR (NOT SEL_0 AND SEL_1 AND CT2(6))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT3A)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(6)));
     XBUS(6) <= XBUS_I(6) when GTS_IN = '1' else 'Z';
XBUS_I(7) <= ((SEL_0 AND SEL_1 AND CT3(7))
      OR (SEL_0 AND NOT SEL_1 AND CT1(7).LFBK)
      OR (NOT SEL_0 AND SEL_1 AND CT2(7))
      OR (NOT SEL_0 AND NOT SEL_1 AND SEL_2 AND NOT CT3B)
      OR (NOT SEL_0 AND NOT SEL_1 AND NOT SEL_2 AND CT0(7)));
     XBUS(7) <= XBUS_I(7) when GTS_IN = '1' else 'Z';
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);